Negative edge detect register port 0/2, Positive mask register port 0/2, Negative mask register port 0/2 – HP E1459A User Manual

Page 85: The positive mask register for port 0/2 (base + 18, The negative mask register for port 0/2 (base + 1a

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84

HP E1459A Register Definitions

Negative Edge

Detect Register Port

0/2

The Negative Edge Detect Register for Port 0/2 (base + 16

h

) is read only.

This register captures any high to low transitions with a "1" in this register
for any channel that has been enabled. A channel is enabled by setting a
corresponding bit in the Negative Mask Register. Once the register is read,
the data is automatically cleared. A transition is only seen if it is held long
enough to pass through the debouncers. If bit 4 of the Control/Status
Register is low ("0"), Port 0 data is accessed. If bit 4 is high ("1"), Port 2
data will be accessed.

Negative Edge Detect Register Port 0/2 (Channels 0-15/32-47) (base + 16h)

Positive Mask

Register Port 0/2

The Positive Mask Register for Port 0/2 (base + 18

h

) can be read or written.

This register enables the Positive Edge Detect Register to capture low to
high transitions on individual channels. When a bit is set to "1" in this
register it enables that channel to be captured in the corresponding bit in the
Positive Edge Detect Register. When a bit is set to "0" it is disabled. If bit
4 of the Control/Status Register is low ("0"), Port 0 data is accessed. If bit
4 is high ("1"), Port 2 data will be accessed.

Positive Mask Register Port 0/2 (Channels 0-15/32-47) (base + 18h)

Negative Mask

Register Port 0/2

The Negative Mask Register for Port 0/2 (base + 1A

h

) can be read or written.

This register enables the Negative Edge Detect Register to capture high to
low transitions on individual channels. When a bit is set to "1" in this register
it enables that channel to be captured in the corresponding bit in the
Negative Edge Detect Register. When a bit is set to "0" it is disabled. If bit
4 of the Control/Status Register is low ("0"), Port 0 data is accessed. If bit 4
is high ("1"), Port 2 data will be accessed.

Negative Mask Register Port 0/2 (Channels 0-15/32-47) (base + 1Ah)

b + 16

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Write

No Effect

Read

Ch15 Ch14 Ch13 Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

Read

Ch47 Ch46 Ch45 Ch44 Ch43 Ch42 Ch41 Ch40 Ch39 Ch38 Ch37 Ch36 Ch35 Ch34 Ch33 Ch32

b + 18

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read/Write Ch15 Ch14 Ch13 Ch12 Ch11 Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

Read/Write Ch47 Ch46 Ch45 Ch44 Ch43 Ch42 Ch41 Ch40 Ch39 Ch38 Ch37 Ch36 Ch35 Ch34 Ch33 Ch32

b + 1A

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read/Write Ch15 Ch14 Ch13 Ch12 Ch11 Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

Read/Write Ch47 Ch46 Ch45 Ch44 Ch43 Ch42 Ch41 Ch40 Ch39 Ch38 Ch37 Ch36 Ch35 Ch34 Ch33 Ch32

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