Document Outline

• V-Series V-Series Avalon-MM DMA Interface for PCIe SolutionsUser Guide
• Contents
• 1. Datasheet
  • V-Series Avalon-MM DMA Interface for PCIe Datasheet
  • Features
  • Release Information
  • V-Series Device Family Support
  • Example Designs
  • Debug Features
  • IP Core Verification
    • Compatibility Testing Environment
  • Performance and Resource Utilization
  • V-Series Recommended Speed Grades
  • Steps in Creating a Design for PCI Express
• 2. Getting Started with the Avalon-MM DMA
  • Generating the Testbench
    • Understanding the Simulation Generated Files
    • Understanding Simulation Log File Generation
  • Simulating the Example Design in ModelSim
  • Running a Gate-Level Simulation
  • Generating Quartus II Synthesis Files
  • Creating a Quartus II Project
  • Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
  • Compiling the Design
  • Descriptor Controller Connectivity when Instantiated Separately
• 3. Parameter Settings
  • System Settings
  • Base Address Register (BAR) Settings
  • Device Identification Registers
  • PCI Express and PCI Capabilities Parameters
    • Device Capabilities
    • Error Reporting
    • Link Capabilities
    • MSI and MSI-X Capabilities
    • Power Management
  • PCIe Address Space Settings
• 4. Interfaces and Signal Descriptions
  • V-Series DMA Avalon-MM DMA Interface to the Application Layer
    • Read DMA Avalon-MM Master Port
    • Write DMA Avalon-MM Master Port
    • RX Master Module
    • TX Slave Module
    • 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
    • Avalon-ST Descriptor Control Interface when Instantiated Separately
      • Avalon-ST Descriptor Status Interface when Instantiated Separately
      • DMA Descriptor Status Bus when Instantiated Separately
    • Descriptor Controller Interfaces when Instantiated Internally
      • Read Descriptor Controller Avalon-MM Master Port
      • Write Descriptor Controller Avalon-MM Master Port
      • Read Descriptor Table Avalon-MM Slave Port
      • Write Descriptor Table Avalon-MM Slave Port
  • Clock Signals
  • Reset, Status, and Link Training Signals
  • MSI Interrupts for Endpoints
  • Physical Layer Interface Signals
    • Transceiver Reconfiguration
    • Serial Data Signals
      • Physical Layout of Hard IP In Arria V GX/GX/SX/ST Devices
      • Channel Placement in Arria V Devices
      • Physical Layout of Hard IP in Cyclone V Devices
      • Channel Placement in Cyclone V Devices
      • Physical Layout of Hard IP in Arria V GZ Devices
      • Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
      • Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
    • PIPE Interface Signals
    • Test Signals
• 5. Registers
  • Correspondence between Configuration Space Registers and the PCIe Specification
  • Type 0 Configuration Space Registers
  • PCI Express Capability Structures
  • Altera-Defined VSEC Registers
  • CvP Registers
  • Uncorrectable Internal Error Mask Register
  • Uncorrectable Internal Error Status Register
  • Correctable Internal Error Mask Register
  • Correctable Internal Error Status Register
  • DMA Descriptor Controller Registers
    • Read DMA and Write DMA Descriptor Format
    • Read DMA Example
    • Software Program for Simultaneous Read and Write DMA
  • Control Register Access (CRA) Avalon-MM Slave Port
• 6. Reset and Clocks
  • Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
  • Clocks
    • Clock Domains
      • pclk
      • coreclkout_hip
      • coreclkout_hip
      • pld_clk
    • Clock Summary
• 7. Error Handling
  • Physical Layer Errors
  • Data Link Layer Errors
  • Transaction Layer Errors
  • Error Reporting and Data Poisoning
  • Uncorrectable and Correctable Error Status Bits
• 8. IP Core Architecture
  • Top-Level Interfaces
    • Avalon-MM DMA Interface
    • Clocks and Reset
    • Transceiver Reconfiguration
    • Interrupts
    • PIPE
  • Data Link Layer
  • Physical Layer
  • V-Series Avalon-MM DMA for PCI Express
• 9. Transceiver PHY IP Reconfiguration
  • Connecting the Transceiver Reconfiguration Controller IP Core
  • Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
• A. Transaction Layer Packet (TLP) Header Formats
  • TLP Packet Formats with Data Payload
• B. Additional Information
  • Revision History for the Avalon-MM Interface with DMA
  • How to Contact Altera
  • Typographic Conventions