Document Outline

• LSI53C140 Ultra2 SCSI Bus Expander
  • Chapter1 Using the LSI53C140
    • 1.1 General Description
      • Figure1.1 LSI53C140 SCSI Bus Modes
      • Figure1.2 LSI53C140 SCSI Bus Modes
      • Table 1.1 Types of Operation
    • 1.2 Applications
      • Figure1.3 LSI53C140 Server Clustering
      • Table 1.2 SCSI Bus Distance Requirements
      • Figure1.4 LSI53C140 SCSI Bus Device
      • Table 1.3 Transmission Mode Distance Requirements
      • 1.2.1 Features
      • 1.2.2 Specifications
    • 1.3 Benefits of LVDlink
  • Chapter2 Functional Descriptions
    • 2.1 Interface Signal Descriptions
      • Figure2.1 LSI53C140 Block Diagram
      • 2.1.1 SCSI A Side and B Side Control Blocks
      • 2.1.2 Retiming Logic
      • 2.1.3 Precision Delay Control
      • 2.1.4 State Machine Control
      • 2.1.5 DIFFSENS Receiver
        • Table 2.1 DIFFSENS Voltage Levels
      • 2.1.6 Dynamic Transmission Mode Changes
    • 2.2 SCSI Signal Descriptions
      • Figure2.2 LSI53C140 Signal Grouping
      • 2.2.1 Data and Parity (SD and SDP)
      • 2.2.2 SCSI Bus Activity LED (BSY_LED)
      • 2.2.3 Select Control (SSEL)
      • 2.2.4 Busy Control (SBSY)
      • 2.2.5 Reset Control (SRST)
      • 2.2.6 Request and Acknowledge Control (SREQ and SACK)
      • 2.2.7 Control/Data, Input/Output, Message, and Attention Controls (SCD, SIO, SMSG, and SATN)
      • 2.2.8 Differential Direction Control
        • Table 2.2 Direction Control Signal Polarity
      • 2.2.9 A and B HVD Mode (A_HVD_MODE and B_HVD_MODE)
        • Table 2.3 HVD_MODE Control Signal Polarities
      • 2.2.10 A and B Differential Sense (A_DIFFSENS and B_DIFFSENS)
        • Table 2.4 Mode Sense Control Voltage Levels
      • 2.2.11 Control Signals
        • Table 2.5 RESET/ Control Signal Polarity
        • Table 2.6 WS_ENABLE/ Signal Polarity
        • Table 2.7 XFER_ACTIVE Signal Polarity
      • 2.2.12 SCSI Termination
  • Chapter3 LSI53C140 Specifications
    • 3.1 General Description
      • Figure3.1 LSI53C140 160-Pin PQFP Pin Diagram
      • Figure3.2 LSI53C140 192-Ball PBGA Top View
      • 3.1.1 Signal Descriptions
        • Figure3.3 LSI53C140 Functional Signal Grouping
        • Table 3.1 SCSI A Side Interface Pins
        • Table 3.2 SCSI B Side Interface Pins
        • Table 3.3 Chip Interface Control Pins
        • Table 3.4 Power and Ground Pins
    • 3.2 Electrical Characteristics
      • 3.2.1 DC Characteristics
        • Table 3.5 Absolute Maximum Stress Ratings
        • Table 3.6 Operating Conditions
        • Table 3.7 LVD Driver SCSI Signals—A_SD[15:0]±, A_SDP[1:0]±, A_SCD±, A_SIO±, A_SMSG±, A_SREQ±, A_S...
        • Figure3.4 LVD Driver
        • Table 3.8 LVD Receiver SCSI Signals—A_SD[15:0]±, A_SDP[1:0]±, A_SCD±, A_SIO±, A_SMSG±, A_SREQ±, A...
        • Figure3.5 LVD Receiver
        • Table 3.9 DIFFSENS SCSI Signal
        • Table 3.10 Input Capacitance
        • Table 3.11 Bidirectional SCSI Signals—A_SD[15:0]±, A_SDP[1:0]±, A_SREQ±, A_SACK±, B_SD[15:0]±, B_...
        • Table 3.12 Bidirectional SCSI Signals—A_SCD±, A_SIO±, A_SMSG±, A_SBSY±, A_SATN±, A_SSEL±, A_SRST±...
        • Table 3.13 Input Control Signals—CLOCK, RESET/, WS_ENABLE
        • Figure3.6 External Reset Circuit
        • Table 3.14 Output Control Signals—BSY_LED, XFER_ACTIVE
      • 3.2.2 TolerANT Technology Electrical Characteristics
        • Table 3.15 TolerANT Technology Electrical Characteristics
        • Figure3.7 Rise and Fall Time Test Conditions
        • Figure3.8 SCSI Input Filtering
        • Figure3.9 Hysteresis of SCSI Receivers
        • Figure3.10 Input Current as a Function of Input Voltage
        • Figure3.11 Output Current as a Function of Output Voltage
      • 3.2.3 AC Characteristics
        • Table 3.16 Clock Timing
        • Figure3.12 Clock Timing
      • 3.2.4 SCSI Interface Timing
        • Table 3.17 Input Timing
        • Table 3.18 Output Timing
        • Figure3.13 Input/Output Timing
    • 3.3 Mechanical Drawings
      • 3.3.1 LSI53C140 160-Pin PQFP Mechanical Drawing
        • Figure3.14 LSI53C140 160-Pin PQFP (PF) Mechanical Drawing
      • 3.3.2 LSI53C140 192-Ball PBGA Mechanical Drawing
        • Figure3.15 192-Ball PBGA (IJ, I2) Mechanical Drawing
  • AppendixA Wiring Diagrams
    • FigureA.1 LSI53C140 Wiring Diagram 1 of 4
    • FigureA.2 LSI53C140 Differential Wiring Diagram
  • AppendixB Board Design Considerations
    • TableB.1 Pin Adjustments
    • TableB.2 No Connect Pins
  • AppendixC Glossary
  • Index
  • Customer Feedback