Document Outline

• 1. Characteristics and specifications
  • Figure 1. Power Up Timing
  • Figure 2. Codec Ready from Start-up or Fault Condition
  • Figure 3. Clocks
  • Figure 4. Data Setup and Hold
  • Figure 5. PR4 Powerdown and Warm Reset
  • Figure 6. Test Mode
• 2. General Description
  • 2.1 AC-Link
    • Figure 7. AC-link Connections
  • 2.2 Control Registers
  • 2.3 Sample Rate Converters
  • 2.4 Mixers
  • 2.5 Input Mux
  • 2.6 Volume Control
  • 2.7 Dedicated Mic Record Path
    • Figure 8. CS4205 Mixer Diagram
• 3. Digital Signal Paths
  • Figure 9. Digital Signal Path Overview
  • 3.1 Analog Centric Mode
  • 3.2 Digital Centric Mode
  • 3.3 Host Processing Mode
  • 3.4 Multi-Channel Mode
    • Table 1. AC Mode Control Configurations
    • Figure 10. Analog Centric Mode
    • Figure 11. Digital Centric Mode
    • Figure 12. Host Processing Mode
    • Figure 13. Multi-Channel Mode
• 4. AC-Link Frame Definition
  • Figure 14. AC-link Input and Output Framing
  • 4.1 AC-Link Serial Data Output Frame
  • 4.2 AC-Link Serial Data Input Frame
  • 4.3 AC-Link Protocol Violation - Loss of SYNC
• 5. Register Interface
  • Table 2. Register Overview for the CS4205
  • Table 3. Indirectly Addressed Register Overview
  • Table 4. Analog Mixer Output Attenuation
  • Table 5. Tone Control Values
  • Table 6. Microphone Input Gain Values
  • Table 7. Analog Mixer Input Gain Values
  • Table 8. Analog Mixer Input Gain Register Index
  • Table 9. Input Mux Selection
  • Table 10. Record Gain Values
  • Table 11. Audio Sample Rate Control Register Index
  • Table 12. Directly Supported SRC Sample Rates for the CS4205
  • Table 13. GPIO Input/Output Configurations
  • Table 14. Slot Mapping for the CS4205
  • Table 15. Digital Signal Source Selects
  • Table 16. Serial Data Format Selection
  • Table 17. Digital Mixer Input Volume Register Index
  • Table 18. Serial Port Volume Control Register Index
  • Table 19. Volume Change Modes and EQ Filter Selects
  • Table 20. Internal Error Sources and Correction Methods
  • Table 21. ZV Port Control/Status Register Index
  • Table 22. Device ID with Corresponding Part Number
• 6. Serial Data Ports
  • 6.1 Overview
  • 6.2 Multi-Channel Expansion
    • Figure 15. Serial Data Port: Six Channel Circuit
  • 6.3 Digital Docking
    • Figure 16. Digital Docking Connection Diagram
  • 6.4 Serial Data Formats
    • Table 23. Serial Data Formats and Compatible DACs/ADC’s for the CS4205
    • Figure 17. Serial Data Format 0 (I2S)
    • Figure 18. Serial Data Format 1 (Left Justified)
    • Figure 19. Serial Data Format 2 (Right Justified, 20-bit data)
    • Figure 20. Serial Data Format 3 (Right Justified, 16-bit data)
• 7. ZV Port
  • Figure 21. ZV Port Format (I2S, 16-bit data)
• 8. Sony/Philips Digital Interface (S/PDIF)
  • Figure 22. S/PDIF Output
• 9. Exclusive Functions
• 10. Power Management
  • 10.1 AC’97 Reset Modes
    • 10.1.1 Cold Reset
    • 10.1.2 Warm Reset
    • 10.1.3 New Warm Reset
    • 10.1.4 Register Reset
  • 10.2 Powerdown Controls
    • Table 24. Powerdown PR Bit Functions
    • Table 25. Powerdown PR Function Matrix for the CS4205
    • Table 26. Power Consumption by Powerdown Mode for the CS4205
• 11. Clocking
  • 11.1 PLL Operation (External Clock)
  • 11.2 24.576 MHz Crystal Operation
  • 11.3 Secondary Codec Operation
    • Figure 23. PLL External Loop Filter
    • Figure 24. External Crystal
    • Table 27. Clocking Configurations for the CS4205
• 12. Analog Hardware DescriptiON
  • 12.1 Analog Inputs
    • 12.1.1 Line Inputs
    • 12.1.2 CD Input
      • Figure 25. Line Input (Replicate for Video and AUX)
      • Figure 26. Differential 2 VRMS CD Input
      • Figure 27. Differential 1 VRMS CD Input
    • 12.1.3 Microphone Inputs
      • Figure 28. Microphone Input
    • 12.1.4 PC Beep Input
      • Figure 29. PC_BEEP Input
    • 12.1.5 Phone Input
      • Figure 30. Modem Connection
  • 12.2 Analog Outputs
    • 12.2.1 Stereo Output
      • Figure 31. Stereo Output
    • 12.2.2 Mono Output
  • 12.3 Miscellaneous Analog Signals
  • 12.4 Power Supplies
    • Figure 32. +5V Analog Voltage Regulator
  • 12.5 Reference Design
• 13. Grounding and Layout
  • Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes
• 14. Pin Descriptions
  • Figure 34. Pin Locations for the CS4205
• 15. Parameter and Term Definitions
• 16. Reference Design
  • Figure 35. CS4205 Reference Design
• 17. References
• 18. Package dimensions