Figure 1. power up timing, Figure 3. clocks, Cs4205 – Cirrus Logic CS4205 User Manual
Page 11
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CS4205
DS489PP4
11
BIT_CLK
T
rst_low
T
rst2clk
T
vdd2rst#
Vdd
RESET#
Figure 1. Power Up Timing
Figure 2. Codec Ready from Start-up or Fault Condition
BIT_CLK
T
sync2crd
CODEC_READY
SYNC
Figure 3. Clocks
BIT_CLK
SYNC
T
irise
T
ifall
T
orise
T
ifall
T
clk_high
T
clk_low
T
sync_high
T
sync_low
T
sync_period
T
clk_period
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