Cirrus Logic CS4205 - Manual (Page 76)

CS4205
76 DS489PP4
These pins provide the supply voltage and ground for the clocking section of the CS4205. In XTAL or
OSC clocking modes DVdd1 should be tied to +5 VD or to +3.3 VD, with DVss1 tied to DGND. In PLL
clocking mode, DVdd1 must be tied to +5 VA and DVss1 must be tied to AGND. If connecting these
pins to +5 VD or to +3.3 VD and DGND, the CS4205 and controller AC-link should share a common
digital supply.
DVdd2, DVss2 - Digital Supply Voltage 2 / Digital Ground 2, Pins 9 and 7
These pins provide the digital supply voltage and digital ground for the AC-link section of the CS4205.
In all clocking modes DVdd2 should be tied to +5 VD or to +3.3 VD, with DVss2 tied to DGND. The
CS4205 and controller AC-link should share a common digital supply. DVss2 should be isolated from
analog ground currents.
AVdd1, AVss1 - Analog Supply Voltage 1 / Analog Ground 1, Pins 25 and 26
These pins provide the analog supply voltage and analog ground for the analog and mixed signal
sections of the CS4205. AVdd1 must be tied to the +5 VA power supply, with AVss1 connected to
AGND. It is strongly recommended the +5 VA power supply be generated from a voltage regulator to
ensure proper supply currents and noise immunity from the rest of the system. AVss2 should be isolated
from digital ground currents
AVdd2, AVss2 - Analog Supply Voltage 2 / Analog Ground 2, Pins 38 and 42
The AVdd2 and AVss2 pins are not used on the CS4205 and may be left floating or tied to +5 VA and
AGND for backwards compatibility