Document Outline

• Front Cover
• FOR SAFE OPERATION
• Revision History
• Preface
• Important Alert Items
• Manual Organization
• Contents
  • Illustrations
    • Figures
    • Tables
• CHAPTER 1 Device Overview
  • 1.1 Features
    • 1.1.1 Functions and performance
    • 1.1.2 Adaptability
    • 1.1.3 Interface
  • 1.2 Device Specifications
    • 1.2.1 Specifications summary
    • 1.2.2 Model and product number
  • 1.3 Power Requirements
  • 1.4 Environmental Specifications
  • 1.5 Acoustic Noise
  • 1.6 Shock and Vibration
  • 1.7 Reliability
  • 1.8 Error Rate
  • 1.9 Media Defects
  • 1.10 Load/Unload Function
  • 1.11 Advanced Power Management
  • 1.12 Interface Power Management (IPM)
    • 1.12.1 Host-initiated Interface Power Management (HIPM)
    • 1.12.2 Device-initiated Interface Power Management (DIPM)
• CHAPTER 2 Device Configuration
  • 2.1 Device Configuration
  • 2.2 System Configuration
    • 2.2.1 SATA interface
    • 2.2.2 Drive connection
• CHAPTER 3 Installation Conditions
  • 3.1 Dimensions
  • 3.2 Mounting
  • 3.3 Connections with Host System
    • 3.3.1 Device connector
    • 3.3.2 Signal segment and power supply segment
    • 3.3.3 Connector specifications for host system
    • 3.3.4 SATA interface cable connection
    • 3.3.5 Note about SATA interface cable connection
• CHAPTER 4 Theory of Device Operation
  • 4.1 Outline
  • 4.2 Subassemblies
    • 4.2.1 Disk
    • 4.2.2 Spindle
    • 4.2.3 Actuator
    • 4.2.4 Air filter
  • 4.3 Circuit Configuration
  • 4.4 Power-on Sequence
  • 4.5 Self-calibration
    • 4.5.1 Self-calibration contents
    • 4.5.2 Execution timing of self-calibration
    • 4.5.3 Command processing during self-calibration
  • 4.6 Read/write Circuit
    • 4.6.1 Read/write preamplifier (PreAMP)
    • 4.6.2 Write circuit
    • 4.6.3 Read circuit
    • 4.6.4 Digital PLL circuit
  • 4.7 Servo Control
    • 4.7.1 Servo control circuit
    • 4.7.2 Data-surface servo format
    • 4.7.3 Servo frame format
    • 4.7.4 Actuator motor control
    • 4.7.5 Spindle motor control
• CHAPTER 5 Interface
  • 5.1 Physical Interface
    • 5.1.1 Interface signals
    • 5.1.2 Signal interface regulation
    • 5.1.3 Electrical specifications
    • 5.1.4 Connector pinouts
  • 5.2 Logical Interface
    • 5.2.1 Communication layers
    • 5.2.2 Outline of the Shadow Block Register
    • 5.2.3 Outline of the frame information structure (FIS)
    • 5.2.4 Shadow block registers
  • 5.3 Host Commands
    • 5.3.1 Command code and parameters
    • 5.3.2 Command descriptions
    • 5.3.3 Error posting
  • 5.4 Command Protocol
    • 5.4.1 Non-data command protocol
    • 5.4.2 PIO data-in command protocol
    • 5.4.3 PIO data-out command protocol
    • 5.4.4 DMA data-in command protocol
    • 5.4.5 DMA data-out command protocol
    • 5.4.6 Native Command Queuing protocol
  • 5.5 Power-on and COMRESET
• CHAPTER 6 Operations
  • 6.1 Reset and Diagnosis
    • 6.1.1 Response to power-on
    • 6.1.2 Response to COMRESET
    • 6.1.3 Response to a software reset
  • 6.2 Power Save
    • 6.2.1 Power save mode
    • 6.2.2 Power commands
  • 6.3 Interface Power Save
    • 6.3.1 Power save mode of the interface
  • 6.4 Read-ahead Cache
    • 6.4.1 Data buffer structure
    • 6.4.2 Caching operation
    • 6.4.3 Using the read segment buffer
  • 6.5 Write Cache
    • 6.5.1 Cache operation
• Glossary
• Acronyms and Abbreviations
• Index
• Comment Form
• Back Cover