Document Outline

• Intel® Xeon™ Processor with 800 MHz System Bus, Intel® E7520 Chipset, and Intel® 6300ESB ICH Development Kit
  • Contents
  • Figures
  • Tables
  • Product Overview 1
    • 1.1 Related Documents
      • Table 1. Related Documents
    • 1.2 Product Contents
    • 1.3 Products Feature List
    • 1.4 Block Diagram
      • Figure 1. Intel® Xeon™ Processor with 800 MHz System Bus and Intel® E7520 and Intel® 6300ESB Customer Reference Board Block Diagram
      • Figure 2. Placement - Top View
      • 1.4.1 Memory Subsystem
        • Table 2. Supported DIMM Module Types
      • 1.4.2 DIMM Placement DDR2 400
        • Table 3. DIMM Placement DDR2 400
    • 1.5 Memory Population Rules and Configurations
      • Figure 3. DDR2 400 Memory - DIMM Ordering
  • Platform Management 2
    • 2.1 Power Button
    • 2.2 Soft Off
    • 2.3 Sleep States Supported
      • 2.3.1 S0 State
      • 2.3.2 S1 State
      • 2.3.3 S2 State
      • 2.3.4 S3 State
      • 2.3.5 S4 State
      • 2.3.6 S5 State
      • 2.3.7 Wake-Up Events
      • 2.3.8 Wake-Up from S1 Sleep State
      • 2.3.9 Wake-Up from S4 and S5 States
    • 2.4 PCI PM Support
    • 2.5 Platform Management
      • 2.5.1 Processor Thermal Management
    • 2.6 System Fan Operation
  • Equipment Required for CRB Usage 3
    • 3.1 Precautions
    • 3.2 Driver and OS Requirements
      • 3.2.1 Drivers included on CD
  • Jumpers and Headers 4
    • 4.1 Jumpers
      • Figure 4. Intel® Xeon™ Processor with 800 MHz System Bus and Intel® E7520 and Intel® 6300ESB Customer Reference Board Jumper
      • Table 4. Jumper Settings (Sheet 1 of 3)
  • System Overview 5
    • 5.1 Power Diagrams
      • Figure 5. Power Distribution Block Diagram
    • 5.2 Platform Clocking
      • Figure 6. Clock Block Diagram
    • 5.3 Platform Resets
      • Figure 7. Platform Reset Diagram
    • 5.4 SMBus
      • Figure 8. SMBus Block Diagram
    • 5.5 Platform IRQ Routing
      • Figure 9. IRQ Routing Diagram
    • 5.6 VRD VID Headers
      • Table 5. Processor VRD Settings (Sheet 1 of 2)
    • 5.7 Miscellaneous Buttons
      • Figure 10. Power Buttons
  • Debug Procedure 6
    • 6.1 Level 1 Debug (Port 80/BIOS)
      • Table 6. Level 1 Debug (Port 80/BIOS)
    • 6.2 Level 2 Debug (Power Sequence)
      • Table 7. Level 2 Debug (Power Sequence)
    • 6.3 Level 3 Debug (Voltage References)
      • Table 8. Level 3 Debug (Voltage References)
  • Heatsink Assembly 7
    • Table 9. Components Requiring Heat Sink Assembly
    • Figure 11. Components Requiring Heat Sink Assembly
    • 7.1 Processor Heat Sink Installation Instructions
      • Figure 12. Inserting Processor in Socket
      • Figure 13. Cleaning the Processor Surface
      • Figure 14. Installing the Processor Backplate
      • Figure 15. Removing the Protective Covers
      • Figure 16. Installing the Heatsink