Document Outline

• Title Page
• Copyright Page
• Contents
  • CHAPTER 1 Introduction
    • 1.3 Electronic Support Systems
      • 1.3.1 FaxBack Service
      • 1.3.2 Bulletin Board System (BBS)
        • 1.3.2.1 How to Find ApBUILDER Software and Hyperte...
      • 1.3.3 CompuServe Forums
      • 1.3.4 World Wide Web
    • 1.4 Technical Support
    • 1.5 Product Literature
    • 1.6 Training Classes
    • 1.1 How to Use This Manual
    • 1.2 Related Documents
  • CHAPTER 2 Overview of the 80C186 Family Architectu...
    • 2.1 Architectural Overview
      • 2.1.1 Execution Unit
      • 2.1.2 Bus Interface Unit
      • 2.1.3 General Registers
      • 2.1.4 Segment Registers
      • 2.1.5 Instruction Pointer
      • 2.1.6 Flags
      • 2.1.7 Memory Segmentation
      • 2.1.8 Logical Addresses
      • 2.1.9 Dynamically Relocatable Code
      • 2.1.10 Stack Implementation
      • 2.1.11 Reserved Memory and I/O Space
    • 2.2 Software Overview
      • 2.2.1 Instruction Set
        • 2.2.1.1 Data Transfer Instructions
        • 2.2.1.2 Arithmetic Instructions
        • 2.2.1.3 Bit Manipulation Instructions
        • 2.2.1.4 String Instructions
        • 2.2.1.5 Program Transfer Instructions
        • 2.2.1.6 Processor Control Instructions
      • 2.2.2 Addressing Modes
        • 2.2.2.1 Register and Immediate Operand Addressing ...
        • 2.2.2.2 Memory Addressing Modes
        • 2.2.2.3 I/O Port Addressing
        • 2.2.2.4 Data Types Used in the 80C186 Modular Core...
    • 2.3 Interrupts and Exception Handling
      • 2.3.1 Interrupt/Exception Processing
        • 2.3.1.1 Non-Maskable Interrupts
        • 2.3.1.2 Maskable Interrupts
        • 2.3.1.3 Exceptions
      • 2.3.2 Software Interrupts
      • 2.3.3 Interrupt Latency
      • 2.3.4 Interrupt Response Time
      • 2.3.5 Interrupt and Exception Priority
  • CHAPTER 3 Bus Interface Unit
    • 3.1 Multiplexed Address and Data Bus
    • 3.2 Address and Data Bus Concepts
      • 3.2.1 16-Bit Data Bus
      • 3.2.2 8-Bit Data Bus
    • 3.3 Memory and I/O Interfaces
      • 3.3.1 16-Bit Bus Memory and I/O Requirements
      • 3.3.2 8-Bit Bus Memory and I/O Requirements
    • 3.4 Bus Cycle Operation
      • 3.4.1 Address/Status Phase
      • 3.4.2 Data Phase
      • 3.4.3 Wait States
      • 3.4.4 Idle States
    • 3.5 Bus Cycles
      • 3.5.1 Read Bus Cycles
        • 3.5.1.1 Refresh Bus Cycles
      • 3.5.2 Write Bus Cycles
      • 3.5.3 Interrupt Acknowledge Bus Cycle
        • 3.5.3.1 System Design Considerations
      • 3.5.4 HALT Bus Cycle
      • 3.5.5 Temporarily Exiting the HALT Bus State
      • 3.5.6 Exiting HALT
    • 3.6 System Design Alternatives
      • 3.6.1 Buffering the Data Bus
      • 3.6.2 Synchronizing Software and Hardware Events
      • 3.6.3 Using a Locked Bus
      • 3.6.4 Using the Queue Status Signals
    • 3.7 Multi-master Bus System Designs
      • 3.7.1 Entering Bus HOLD
        • 3.7.1.1 HOLD Bus Latency
        • 3.7.1.2 Refresh Operation During a Bus HOLD
      • 3.7.2 Exiting HOLD
    • 3.8 Bus Cycle Priorities
  • CHAPTER 4 Peripheral Control Block
    • 4.1 Peripheral Control Registers
    • 4.2 PCB Relocation Register
    • 4.3 Reserved Locations
    • 4.4 Accessing the Peripheral Control Block
      • 4.4.1 Bus Cycles
      • 4.4.2 READY Signals and Wait States
      • 4.4.3 F-Bus Operation
        • 4.4.3.1 Writing the PCB Relocation Register
        • 4.4.3.2 Accessing the Peripheral Control Registers...
        • 4.4.3.3 Accessing Reserved Locations
    • 4.5 Setting the PCB Base Location
      • 4.5.1 Considerations for the 80C187 Math Coprocess...
  • CHAPTER 5 Clock Generation and Power Management
    • 5.1 Clock Generation
      • 5.1.1 Crystal Oscillator
        • 5.1.1.1 Oscillator Operation
        • 5.1.1.2 Selecting Crystals
      • 5.1.2 Using an External Oscillator
      • 5.1.3 Output from the Clock Generator
      • 5.1.4 Reset and Clock Synchronization
    • 5.2 Power Management
      • 5.2.1 Power-Save Mode
        • 5.2.1.1 Entering Power-Save Mode
      • 5.2.1.2 Leaving Power-Save Mode
      • 5.2.1.3 Example Power-Save Initialization Code
        • Example 51. Initializing the Power Management Uni...
  • CHAPTER 6 Chip-Select Unit
    • 6.1 Common Methods for Generating Chip-Selects
    • 6.2 Chip-Select Unit Features and Benefits
    • 6.3 Chip-Select Unit Functional Overview
    • 6.4 Programming
      • 6.4.1 Initialization Sequence
      • 6.4.2 Programming the Active Ranges
        • 6.4.2.1 UCS Active Range
        • 6.4.2.2 LCS Active Range
        • 6.4.2.3 MCS Active Range
        • 6.4.2.4 PCS Active Range
      • 6.4.3 Bus Wait State and Ready Control
      • 6.4.4 Overlapping Chip-Selects
      • 6.4.5 Memory or I/O Bus Cycle Decoding
      • 6.4.6 Programming Considerations
    • 6.5 Chip-Selects And Bus Hold
    • 6.6 Examples
      • 6.6.1 Example 1: Typical System Configuration
        • Example 61. Initializing the Chip-Select Unit
  • CHAPTER 7 Refresh Control Unit
    • 7.1 The Role of the Refresh Control Unit
    • 7.2 Refresh Control Unit Capabilities
    • 7.3 Refresh Control Unit Operation
    • 7.4 Refresh Addresses
    • 7.5 Refresh Bus Cycles
    • 7.6 Guidelines for Designing DRAM Controllers
    • 7.7 Programming the Refresh Control Unit
      • 7.7.1 Calculating the Refresh Interval
      • 7.7.2 Refresh Control Unit Registers
        • 7.7.2.1 Refresh Base Address Register
        • 7.7.2.2 Refresh Clock Interval Register
        • 7.7.2.3 Refresh Control Register
      • 7.7.3 Programming Example
        • Example 71. Initializing the Refresh Control Unit...
    • 7.8 Refresh Operation and Bus HOLD
  • CHAPTER 8 Interrupt Control Unit
    • 8.1 Functional Overview
    • 8.2 Master Mode
      • 8.2.1 Generic Functions in Master Mode
        • 8.2.1.1 Interrupt Masking
        • 8.2.1.2 Interrupt Priority
        • 8.2.1.3 Interrupt Nesting
      • 8.3 Functional Operation In Master Mode
        • 8.3.1 Typical Interrupt Sequence
        • 8.3.2 Priority Resolution
          • 8.3.2.1 Priority Resolution Example
          • 8.3.2.2 Interrupts That Share a Single Source
        • 8.3.3 Cascading with External 8259As
          • 8.3.3.1 Special Fully Nested Mode
        • 8.3.4 Interrupt Acknowledge Sequence
        • 8.3.5 Polling
        • 8.3.6 Edge and Level Triggering
        • 8.3.7 Additional Latency and Response Time
      • 8.4 Programming the Interrupt Control Unit
        • 8.4.1 Interrupt Control Registers
        • 8.4.2 Interrupt Request Register
        • 8.4.3 Interrupt Mask Register
        • 8.4.4 Priority Mask Register
        • 8.4.5 In-Service Register
        • 8.4.6 Poll and Poll Status Registers
        • 8.4.7 End-of-Interrupt (EOI) Register
        • 8.4.8 Interrupt Status Register
      • 8.5 Slave Mode
        • 8.5.1 Slave Mode Programming
          • 8.5.1.1 Interrupt Vector Register
          • 8.5.1.2 End-Of-Interrupt Register
          • 8.5.1.3 Other Registers
        • 8.5.2 Interrupt Vectoring in Slave Mode
        • 8.5.3 Initializing the Interrupt Control Unit for ...
          • Example 81. Initializing the Interrupt Control Un...
  • CHAPTER 9 Timer/Counter Unit
    • 9.1 Functional Overview
    • 9.2 Programming the Timer/Counter Unit
      • 9.2.1 Initialization Sequence
      • 9.2.2 Clock Sources
      • 9.2.3 Counting Modes
        • 9.2.3.1 Retriggering
      • 9.2.4 Pulsed and Variable Duty Cycle Output
      • 9.2.5 Enabling/Disabling Counters
      • 9.2.6 Timer Interrupts
      • 9.2.7 Programming Considerations
    • 9.3 Timing
      • 9.3.1 Input Setup and Hold Timings
      • 9.3.2 Synchronization and Maximum Frequency
        • 9.3.2.1 Timer/Counter Unit Application Examples
      • 9.3.3 Real-Time Clock
      • 9.3.4 Square-Wave Generator
      • 9.3.5 Digital One-Shot
        • Example 91. Configuring a Real-Time Clock
        • Example 92. Configuring a Square-Wave Generator
        • Example 93. Configuring a Digital One-Shot
  • CHAPTER 10 Direct Memory Access Unit
    • 10.1 Functional Overview
      • 10.1.1 The DMA Transfer
        • 10.1.1.1 DMA Transfer Directions
        • 10.1.1.2 Byte and Word Transfers
      • 10.1.2 Source and Destination Pointers
      • 10.1.3 DMA Requests
      • 10.1.4 External Requests
        • 10.1.4.1 Source Synchronization
        • 10.1.4.2 Destination Synchronization
      • 10.1.5 Internal Requests
        • 10.1.5.2 Unsynchronized Transfers
      • 10.1.6 DMA Transfer Counts
      • 10.1.7 Termination and Suspension of DMA Transfers...
        • 10.1.7.1 Termination at Terminal Count
        • 10.1.7.2 Software Termination
        • 10.1.7.3 Suspension of DMA During NMI
        • 10.1.7.4 Software Suspension
      • 10.1.8 DMA Unit Interrupts
      • 10.1.9 DMA Cycles and the BIU
      • 10.1.10 The Two-Channel DMA Unit
        • 10.1.10.1 DMA Channel Arbitration
          • 10.1.10.1.1 Fixed Priority
          • 10.1.10.1.2 Rotating Priority
    • 10.2 Programming the DMA Unit
      • 10.2.1 DMA Channel Parameters
        • 10.2.1.1 Programming the Source and Destination Po...
        • 10.2.1.2 Selecting Byte or Word Size Transfers
        • 10.2.1.3 Selecting the Source of DMA Requests
        • 10.2.1.4 Arming the DMA Channel
        • 10.2.1.5 Selecting Channel Synchronization
        • 10.2.1.6 Programming the Transfer Count Options
        • 10.2.1.7 Generating Interrupts on Terminal Count
        • 10.2.1.8 Setting the Relative Priority of a Channe...
      • 10.2.2 Suspension of DMA Transfers
      • 10.2.3 Initializing the DMA Unit
    • 10.3 Hardware Considerations and the Dma Unit
      • 10.3.1 DRQ Pin Timing Requirements
      • 10.3.2 DMA Latency
      • 10.3.3 DMA Transfer Rates
      • 10.3.4 Generating a DMA Acknowledge
    • 10.4 DMA Unit Examples
      • Example 101. Initializing the DMA Unit
      • Example 102. Timed DMA Transfers
  • CHAPTER 11 Math Coprocessing
    • 11.1 Overview of Math Coprocessing
    • 11.2 Availability of Math Coprocessing
    • 11.3 The 80c187 Math Coprocessor
      • 11.3.1 80C187 Instruction Set
        • 11.3.1.1 Data Transfer Instructions
        • 11.3.1.2 Arithmetic Instructions
        • 11.3.1.3 Comparison Instructions
        • 11.3.1.4 Transcendental Instructions
        • 11.3.1.5 Constant Instructions
        • 11.3.1.6 Processor Control Instructions
      • 11.3.2 80C187 Data Types
    • 11.4 Microprocessor and Coprocessor Operation
      • 11.4.1 Clocking the 80C187
      • 11.4.2 Processor Bus Cycles Accessing the 80C187
      • 11.4.3 System Design Tips
      • 11.4.4 Exception Trapping
    • 11.5 Example Math Coprocessor Routines
      • Example 111. Initialization Sequence for 80C187 M...
      • Example 112. Floating Point Math Routine Using FS...
  • CHAPTER 12 Once Mode
    • 12.1 Entering/Leaving Once Mode
  • APPENDIX A 80C186 Instruction Set Additions and Ex...
    • A.1 80C186 Instruction Set Additions
      • A.1.1 Data Transfer Instructions
      • A.1.2 String Instructions
      • A.1.3 High-Level Instructions
    • A.2 80C186 Instruction Set Enhancements
      • A.2.1 Data Transfer Instructions
      • A.2.2 Arithmetic Instructions
      • A.2.3 Bit Manipulation Instructions
        • A.2.3.1 Shift Instructions
        • A.2.3.2 Rotate Instructions
  • APPENDIX B Input Synchronization
    • B.1 Why Synchronizers are Required
    • B.2 Asynchronous Pins
  • APPENDIX C Instruction Set Descriptions
  • APPENDIX D Instruction Set Opcodes and Clock Cycle...
  • Figures
    • Figure 21. Simplified Functional Block Diagram of...
    • Figure 22. Physical Address Generation
    • Figure 23. General Registers
    • Figure 24. Segment Registers
    • Figure 25. Processor Status Word
    • Figure 26. Segment Locations in Physical Memory
    • Figure 27. Currently Addressable Segments
    • Figure 28. Logical and Physical Address
    • Figure 29. Dynamic Code Relocation
    • Figure 210. Stack Operation
    • Figure 211. Flag Storage Format
    • Figure 212. Memory Address Computation
    • Figure 213. Direct Addressing
    • Figure 214. Register Indirect Addressing
    • Figure 215. Based Addressing
    • Figure 216. Accessing a Structure with Based Addr...
    • Figure 217. Indexed Addressing
    • Figure 218. Accessing an Array with Indexed Addre...
    • Figure 219. Based Index Addressing
    • Figure 220. Accessing a Stacked Array with Based ...
    • Figure 221. String Operand
    • Figure 222. I/O Port Addressing
    • Figure 223. 80C186 Modular Core Family Supported ...
    • Figure 224. Interrupt Control Unit
    • Figure 225. Interrupt Vector Table
    • Figure 226. Interrupt Sequence
    • Figure 227. Interrupt Response Factors
    • Figure 228. Simultaneous NMI and Exception
    • Figure 229. Simultaneous NMI and Single Step Inte...
    • Figure 230. Simultaneous NMI, Single Step and Mas...
    • Figure 31. Physical Data Bus Models
    • Figure 32. 16-Bit Data Bus Byte Transfers
    • Figure 33. 16-Bit Data Bus Even Word Transfers
    • Figure 34. 16-Bit Data Bus Odd Word Transfers
    • Figure 35. 8-Bit Data Bus Word Transfers
    • Figure 36. Typical Bus Cycle
    • Figure 37. T-State Relation to CLKOUT
    • Figure 38. BIU State Diagram
    • Figure 39. T-State and Bus Phases
    • Figure 310. Address/Status Phase Signal Relations...
    • Figure 311. Demultiplexing Address Information
    • Figure 312. Data Phase Signal Relationships
    • Figure 313. Typical Bus Cycle with Wait States
    • Figure 314. ARDY and SRDY Pin Block Diagram
    • Figure 315. Generating a Normally Not-Ready Bus S...
    • Figure 316. Generating a Normally Ready Bus Signa...
    • Figure 317. Normally Not-Ready System Timing
    • Figure 318. Normally Ready System Timings
    • Figure 319. Typical Read Bus Cycle
    • Figure 320. Read-Only Device Interface
    • Figure 321. Typical Write Bus Cycle
    • Figure 322. 16-Bit Bus Read/Write Device Interfac...
    • Figure 323. Interrupt Acknowledge Bus Cycle
    • Figure 324. Typical 82C59A Interface
    • Figure 325. HALT Bus Cycle
    • Figure 326. Returning to HALT After a HOLD/HLDA B...
    • Figure 327. Returning to HALT After a Refresh Bus...
    • Figure 328. Returning to HALT After a DMA Bus Cyc...
    • Figure 329. Exiting HALT
    • Figure 330. DEN and DT/R Timing Relationships
    • Figure 331. Buffered AD Bus System
    • Figure 332. Qualifying DEN with Chip-Selects
    • Figure 333. Queue Status Timing
    • Figure 334. Timing Sequence Entering HOLD
    • Figure 335. Refresh Request During HOLD
    • Figure 336. Latching HLDA
    • Figure 337. Exiting HOLD
    • Figure 41. PCB Relocation Register
    • Figure 51. Clock Generator
    • Figure 52. Ideal Operation of Pierce Oscillator
    • Figure 53. Crystal Connections to Microprocessor
    • Figure 54. Equations for Crystal Calculations
    • Figure 55. Simple RC Circuit for Powerup Reset
    • Figure 56. Cold Reset Waveform
    • Figure 57. Warm Reset Waveform
    • Figure 58. Clock Synchronization at Reset
    • Figure 59. Power-Save Register
    • Figure 510. Power-Save Clock Transition
    • Figure 61. Common Chip-Select Generation Methods
    • Figure 62. Chip-Select Block Diagram
    • Figure 63. Chip-Select Relative Timings
    • Figure 64. UCS Reset Configuration
    • Figure 65. UMCS Register Definition
    • Figure 66. LMCS Register Definition
    • Figure 67. MMCS Register Definition
    • Figure 68. PACS Register Definition
    • Figure 69. MPCS Register Definition
    • Figure 610. MCS3:0 Active Ranges
    • Figure 611. Wait State and Ready Control Function...
    • Figure 612. Using Chip-Selects During HOLD
    • Figure 613. Typical System
    • Figure 71. Refresh Control Unit Block Diagram
    • Figure 72. Refresh Control Unit Operation Flow Ch...
    • Figure 73. Refresh Address Formation
    • Figure 74. Suggested DRAM Control Signal Timing R...
    • Figure 75. Formula for Calculating Refresh Interv...
    • Figure 76. Refresh Base Address Register
    • Figure 77. Refresh Clock Interval Register
    • Figure 78. Refresh Control Register
    • Figure 79. Regaining Bus Control to Run a DRAM Re...
    • Figure 81. Interrupt Control Unit in Master Mode
    • Figure 82. Using External 8259A Modules in Cascad...
    • Figure 83. Interrupt Control Unit Latency and Res...
    • Figure 84. Interrupt Control Register for Interna...
    • Figure 85. Interrupt Control Register for Noncasc...
    • Figure 86. Interrupt Control Register for Cascada...
    • Figure 87. Interrupt Request Register
    • Figure 88. Interrupt Mask Register
    • Figure 89. Priority Mask Register
    • Figure 810. In-Service Register
    • Figure 811. Poll Register
    • Figure 812. Poll Status Register
    • Figure 813. End-of-Interrupt Register
    • Figure 814. Interrupt Status Register
    • Figure 815. Interrupt Control Unit in Slave Mode
    • Figure 816. Interrupt Sources in Slave Mode
    • Figure 817. Interrupt Vector Register (Slave Mode...
    • Figure 818. End-of-Interrupt Register in Slave Mo...
    • Figure 819. Request, Mask, and In-Service Registe...
    • Figure 820. Interrupt Vectoring in Slave Mode
    • Figure 821. Interrupt Response Time in Slave Mode...
    • Figure 91. Timer/Counter Unit Block Diagram
    • Figure 92. Counter Element Multiplexing and Timer...
    • Figure 93. Timers 0 and 1 Flow Chart
    • Figure 93. Timers 0 and 1 Flow Chart (Continued)
    • Figure 94. Timer/Counter Unit Output Modes
    • Figure 95. Timer 0 and Timer 1 Control Registers
    • Figure 95. Timer 0 and Timer 1 Control Registers ...
    • Figure 96. Timer 2 Control Register
    • Figure 97. Timer Count Registers
    • Figure 98. Timer Maxcount Compare Registers
    • Figure 99. TxOUT Signal Timing
    • Figure 101. Typical DMA Transfer
    • Figure 102. DMA Request Minimum Response Time
    • Figure 103. Source-Synchronized Transfers
    • Figure 104. Destination-Synchronized Transfers
    • Figure 105. Two-Channel DMA Module
    • Figure 106. Examples of DMA Priority
    • Figure 107. DMA Source Pointer (High-Order Bits)
    • Figure 108. DMA Source Pointer (Low-Order Bits)
    • Figure 109. DMA Destination Pointer (High-Order B...
    • Figure 1010. DMA Destination Pointer (Low-Order B...
    • Figure 1011. DMA Control Register
    • Figure 1011. DMA Control Register (Continued)
    • Figure 1011. DMA Control Register (Continued)
    • Figure 1012. Transfer Count Register
    • Table 116. 80C187 Processor Control Instructions ...
    • Figure 111. 80C187-Supported Data Types
    • Figure 112. 80C186 Modular Core Family/80C187 Sys...
    • Figure 113. 80C187 Configuration with a Partially...
    • Figure 114. 80C187 Exception Trapping via Process...
    • Figure 121. Entering/Leaving ONCE Mode
    • Figure A1. Formal Definition of ENTER
    • Figure A2. Variable Access in Nested Procedures
    • Figure A3. Stack Frame for Main at Level 1
    • Figure A4. Stack Frame for Procedure A at Level 2...
    • Figure A5. Stack Frame for Procedure B at Level 3...
    • Figure A6. Stack Frame for Procedure C at Level 3...
    • Figure B1. Input Synchronization Circuit
  • Tables
    • Table 11. Comparison of 80C186 Modular Core Famil...
    • Table 12. Related Documents and Software(Continu...
    • Table 21. Implicit Use of General Registers
    • Table 22. Logical Address Sources 
    • Table 23. Data Transfer Instructions 
    • Table 24. Arithmetic Instructions 
    • Table 25. Arithmetic Interpretation of 8-Bit Numb...
    • Table 26. Bit Manipulation Instructions 
    • Table 27. String Instructions 
    • Table 28. String Instruction Register and Flag Us...
    • Table 29. Program Transfer Instructions 
    • Table 210. Interpretation of Conditional Transfer...
    • Table 211. Processor Control Instructions
    • Table 212. Supported Data Types 
    • Table 31. Bus Cycle Types 
    • Table 32. Read Bus Cycle Types 
    • Table 33. Read Cycle Critical Timing Parameters ...
    • Table 34. Write Bus Cycle Types
    • Table 35. Write Cycle Critical Timing Parameters ...
    • Table 36. HALT Bus Cycle Pin States
    • Table 37. Queue Status Signal Decoding
    • Table 38. Signal Condition Entering HOLD 
    • Table 41. Peripheral Control Block
    • Table 51. Suggested Values for Inductor L1 in Thi...
    • Table 61. Chip-Select Unit Registers 
    • Table 62. UCS Block Size and Starting Address
    • Table 6 3. LCS Active Range
    • Table 64. MCS Active Range
    • Table 65. MCS Block Size and Start Address Restri...
    • Table 66. PCS Active Range
    • Table 71. Identification of Refresh Bus Cycles 
    • Table 81. Default Interrupt Priorities 
    • Table 82. Fixed Interrupt Types
    • Table 83. Interrupt Control Unit Registers in Mas...
    • Table 84. Interrupt Control Unit Register Compari...
    • Table 85. Slave Mode Fixed Interrupt Type Bits
    • Table 91. Timer 0 and 1 Clock Sources
    • Table 92. Timer Retriggering
    • Table 111. 80C187 Data Transfer Instructions
    • Table 112. 80C187 Arithmetic Instructions 
    • Table 113. 80C187 Comparison Instructions 
    • Table 114. 80C187 Transcendental Instructions 
    • Table 115. 80C187 Constant Instructions
    • Table 117. 80C187 I/O Port Assignments
    • Table C1. Instruction Format Variables
    • Table C2. Instruction Operands
    • Table C3. Flag Bit Functions
    • Table C4. Instruction Set (Continued)
    • Table D1. Operand Variables
    • Table D2. Instruction Set Summary (Continued)
    • Table D3. Machine Instruction Decoding Guide (Con...
    • Table D4. Mnemonic Encoding Matrix (Left Half)
    • Table D4. Mnemonic Encoding Matrix (Right Half)
    • Table D5. Abbreviations for Mnemonic Encoding Mat...