Document Outline

• NI 5401 User Manual
• Support
  • Worldwide Technical Support and Product Information
  • National Instruments Corporate Headquarters
  • Worldwide Offices
• Important Information
  • Warranty
  • Copyright
  • Trademarks
  • WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS
• Conventions
• Contents
• Chapter 1 Generating Functions with the NI 5401
  • About Your NI 5401
  • Connecting Signals
    • ARB Connector
    • SYNC Connector
    • PLL Ref Connector
    • Pattern Out Connector (PCI Only)
      • Connector Pin Assignments
      • Signal Descriptions
    • SHC50-68 50-Pin Cable Connector
  • Software Options for Your NI 5401
    • Software Included with Your NI 5401
      • VirtualBench
      • NI-FGEN Instrument Driver
    • Additional National Instruments Development Tools
      • LabVIEW
      • LabWindows/CVI
      • ComponentWorks
  • Using the Soft Front Panels to Generate Waveforms
    • Generating Standard Functions
    • Generating Multiple Frequencies in a Sequence
    • Waveform Editor
  • Power-Up and Reset Conditions
• Chapter 2 Function Generator Operation
  • Generating Waveforms
  • Direct Digital Synthesis (DDS)
    • Frequency Hopping and Sweeping
  • Triggering
    • Trigger Sources
    • Modes of Operation
      • Single Trigger Mode
      • Continuous Trigger Mode
      • Stepped Trigger Mode
  • Analog Output
    • SYNC Output and Duty Cycle
    • Output Attenuation
    • Output Impedance
    • Output Enable
    • Pre-Attenuation Offset
  • Phase-Locked Loops and Board Synchronization
  • Analog Filter Correction
  • RTSI/PXI Trigger Lines
  • Calibration
• Appendix A Specifications
  • Analog Output
  • Voltage Output
  • Triggers
  • Bus Interface
  • Operational Modes
  • SYNC Out
  • External Clock Reference Input
  • Internal Clock
  • Mechanical
• Appendix B Optional Accessories
  • Cabling
• Appendix C Frequency Resolution and Lookup Memory
• Appendix D Technical Support Resources
  • NI Web Support
    • On-Line Problem-Solving and Diagnostic Resources
    • Software-Related Resources
  • Worldwide Support
• Glossary
  • Numbers/Symbols
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
  • K
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • V
  • W
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • V
  • W
• Figures
  • Figure 1-1. NI 5401 I/O Connectors
  • Figure 1-2. Output Levels and Load Termination Using a 50 W Output Impedance
  • Figure 1-3. SYNC Output and Duty Cycle
  • Figure 1-4. NI 5401 50-Pin Digital Connector Pin Assignments
  • Figure 1-5. SHC50-68 68-Pin Connector Pin Assignments
  • Figure 1-6. VirtualBench-FG Soft Front Panel for Function Generation
  • Figure 1-7. VirtualBench-FG General Settings Dialog Box for the NI 5401
  • Figure 1-8. VirtualBench-FG Signals Settings Dialog Box for the NI 5401
  • Figure 1-9. VirtualBench-FG Load Waveform Dialog Box
  • Figure 1-10. VirtualBench-FG Frequency List Editor Dialog Box
  • Figure 1-11. Waveform Editor Soft Front Panel
  • Figure 2-1. NI 5401 Block Diagram
  • Figure 2-2. Waveform Data Path Block Diagram
  • Figure 2-3. DDS Building Blocks
  • Figure 2-4. Waveform Generation Trigger Sources
  • Figure 2-5. Single Trigger Mode
  • Figure 2-6. Continuous Trigger Mode
  • Figure 2-7. Stepped Trigger Mode
  • Figure 2-8. Analog Output and SYNC Out Block Diagram
  • Figure 2-9. Waveform and Trigger Timings
  • Figure 2-10. Output Attenuation Chain
  • Figure 2-11. PLL Architecture for the NI 5401 for PCI
  • Figure 2-12. PLL Architecture for the NI 5401 for PXI
  • Figure 2-13. Analog Filter Correction
  • Figure 2-14. RTSI Trigger Lines and Routing for the NI 5401 for PCI
  • Figure 2-15. PXI Trigger Lines, 10 MHz Backplane Oscillator, and Routing for the NI 5401 for PXI
• Table
  • Table 1-1. Digital Connector Signal Descriptions