Document Outline

• Features
• Pin Configurations
  • Disclaimer
• Overview
  • Block Diagram
  • Pin Descriptions
    • VCC
    • GND
    • Port A (PA7..PA0)
    • Port B (PB7..PB0)
    • Port C (PC7..PC0)
    • Port D (PD7..PD0)
    • Port E (PE7..PE0)
    • Port F (PF7..PF0)
    • Port G (PG5..PG0)
    • RESET
    • XTAL1
    • XTAL2
    • AVCC
    • AREF
• About Code Examples
• AVR CPU Core
  • Introduction
  • Architectural Overview
  • ALU – Arithmetic Logic Unit
  • Status Register
  • General Purpose Register File
    • The X-register, Y-register, and Z-register
  • Stack Pointer
  • Instruction Execution Timing
  • Reset and Interrupt Handling
    • Interrupt Response Time
• AVR ATmega169 Memories
  • In-System Reprogrammable Flash Program Memory
  • SRAM Data Memory
    • Data Memory Access Times
  • EEPROM Data Memory
    • EEPROM Read/Write Access
    • The EEPROM Address Register – EEARH and EEARL
    • The EEPROM Data Register – EEDR
    • The EEPROM Control Register – EECR
    • Preventing EEPROM Corruption
  • I/O Memory
    • General Purpose I/O Registers
    • General Purpose I/O Register 2 – GPIOR2
    • General Purpose I/O Register 1 – GPIOR1
    • General Purpose I/O Register 0 – GPIOR0
• System Clock and Clock Options
  • Clock Systems and their Distribution
    • CPU Clock – clkCPU
    • I/O Clock – clkI/O
    • Flash Clock – clkFLASH
    • Asynchronous Timer Clock – clkASY
    • ADC Clock – clkADC
  • Clock Sources
  • Default Clock Source
  • Crystal Oscillator
  • Low-frequency Crystal Oscillator
  • Calibrated Internal RC Oscillator
    • Oscillator Calibration Register – OSCCAL
  • External Clock
  • Clock Output Buffer
  • Timer/Counter Oscillator
  • System Clock Prescaler
    • Clock Prescale Register – CLKPR
• Power Management and Sleep Modes
  • Sleep Mode Control Register – SMCR
  • Idle Mode
  • ADC Noise Reduction Mode
  • Power-down Mode
  • Power-save Mode
  • Standby Mode
  • Minimizing Power Consumption
    • Analog to Digital Converter
    • Analog Comparator
    • Brown-out Detector
    • Internal Voltage Reference
    • Watchdog Timer
    • Port Pins
• System Control and Reset
  • Resetting the AVR
  • Reset Sources
  • Power-on Reset
  • External Reset
  • Brown-out Detection
  • Watchdog Reset
  • MCU Status Register – MCUSR
  • Internal Voltage Reference
    • Voltage Reference Enable Signals and Start-up Time
  • Watchdog Timer
    • Watchdog Timer Control Register – WDTCR
  • Timed Sequences for Changing the Configuration of the Watchdog Timer
    • Safety Level 1
    • Safety Level 2
• Interrupts
  • Interrupt Vectors in ATmega169
    • Moving Interrupts Between Application and Boot Space
    • MCU Control Register – MCUCR
• I/O-Ports
  • Introduction
  • Ports as General Digital I/O
    • Configuring the Pin
    • Toggling the Pin
    • Switching Between Input and Output
    • Reading the Pin Value
    • Digital Input Enable and Sleep Modes
  • Alternate Port Functions
    • MCU Control Register – MCUCR
    • Alternate Functions of Port A
    • Alternate Functions of Port B
    • Alternate Functions of Port C
    • Alternate Functions of Port D
    • Alternate Functions of Port E
    • Alternate Functions of Port F
    • Alternate Functions of Port G
  • Register Description for I/O-Ports
    • Port A Data Register – PORTA
    • Port A Data Direction Register – DDRA
    • Port A Input Pins Address – PINA
    • Port B Data Register – PORTB
    • Port B Data Direction Register – DDRB
    • Port B Input Pins Address – PINB
    • Port C Data Register – PORTC
    • Port C Data Direction Register – DDRC
    • Port C Input Pins Address – PINC
    • Port D Data Register – PORTD
    • Port D Data Direction Register – DDRD
    • Port D Input Pins Address – PIND
    • Port E Data Register – PORTE
    • Port E Data Direction Register – DDRE
    • Port E Input Pins Address – PINE
    • Port F Data Register – PORTF
    • Port F Data Direction Register – DDRF
    • Port F Input Pins Address – PINF
    • Port G Data Register – PORTG
    • Port G Data Direction Register – DDRG
    • Port G Input Pins Address – PING
• External Interrupts
  • External Interrupt Control Register A – EICRA
  • External Interrupt Mask Register – EIMSK
  • External Interrupt Flag Register – EIFR
  • Pin Change Mask Register 1 – PCMSK1
  • Pin Change Mask Register 0 – PCMSK0
• 8-bit Timer/Counter0 with PWM
  • Overview
    • Registers
    • Definitions
  • Timer/Counter Clock Sources
  • Counter Unit
  • Output Compare Unit
    • Force Output Compare
    • Compare Match Blocking by TCNT0 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 8-bit Timer/Counter Register Description
    • Timer/Counter Control Register A – TCCR0A
    • Timer/Counter Register – TCNT0
    • Output Compare Register A – OCR0A
    • Timer/Counter 0 Interrupt Mask Register – TIMSK0
    • Timer/Counter 0 Interrupt Flag Register – TIFR0
• Timer/Counter0 and Timer/Counter1 Prescalers
  • Internal Clock Source
  • Prescaler Reset
  • External Clock Source
  • General Timer/Counter Control Register – GTCCR
• 16-bit Timer/Counter1
  • Overview
    • Registers
    • Definitions
    • Compatibility
  • Accessing 16-bit Registers
    • Reusing the Temporary High Byte Register
  • Timer/Counter Clock Sources
  • Counter Unit
  • Input Capture Unit
    • Input Capture Trigger Source
    • Noise Canceler
    • Using the Input Capture Unit
  • Output Compare Units
    • Force Output Compare
    • Compare Match Blocking by TCNT1 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
    • Phase and Frequency Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 16-bit Timer/Counter Register Description
    • Timer/Counter1 Control Register A – TCCR1A
    • Timer/Counter1 Control Register B – TCCR1B
    • Timer/Counter1 Control Register C – TCCR1C
    • Timer/Counter1 – TCNT1H and TCNT1L
    • Output Compare Register 1 A – OCR1AH and OCR1AL
    • Output Compare Register 1 B – OCR1BH and OCR1BL
    • Input Capture Register 1 – ICR1H and ICR1L
    • Timer/Counter1 Interrupt Mask Register – TIMSK1
    • Timer/Counter1 Interrupt Flag Register – TIFR1
• 8-bit Timer/Counter2 with PWM and Asynchronous Operation
  • Overview
    • Registers
    • Definitions
  • Timer/Counter Clock Sources
  • Counter Unit
  • Output Compare Unit
    • Force Output Compare
    • Compare Match Blocking by TCNT2 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 8-bit Timer/Counter Register Description
    • Timer/Counter Control Register A– TCCR2A
    • Timer/Counter Register – TCNT2
    • Output Compare Register A – OCR2A
  • Asynchronous operation of the Timer/Counter
    • Asynchronous Status Register – ASSR
    • Asynchronous Operation of Timer/Counter2
    • Timer/Counter2 Interrupt Mask Register – TIMSK2
    • Timer/Counter2 Interrupt Flag Register – TIFR2
  • Timer/Counter Prescaler
    • General Timer/Counter Control Register – GTCCR
• Serial Peripheral Interface – SPI
  • SS Pin Functionality
    • Slave Mode
    • Master Mode
    • SPI Control Register – SPCR
    • SPI Status Register – SPSR
    • SPI Data Register – SPDR
  • Data Modes
• USART
  • Overview
    • AVR USART vs. AVR UART – Compatibility
  • Clock Generation
    • Internal Clock Generation – The Baud Rate Generator
    • Double Speed Operation (U2X)
    • External Clock
    • Synchronous Clock Operation
  • Frame Formats
    • Parity Bit Calculation
  • USART Initialization
  • Data Transmission – The USART Transmitter
    • Sending Frames with 5 to 8 Data Bit
    • Sending Frames with 9 Data Bit
    • Transmitter Flags and Interrupts
    • Parity Generator
    • Disabling the Transmitter
  • Data Reception – The USART Receiver
    • Receiving Frames with 5 to 8 Data Bits
    • Receiving Frames with 9 Data Bits
    • Receive Compete Flag and Interrupt
    • Receiver Error Flags
    • Parity Checker
    • Disabling the Receiver
    • Flushing the Receive Buffer
  • Asynchronous Data Reception
    • Asynchronous Clock Recovery
    • Asynchronous Data Recovery
    • Asynchronous Operational Range
  • Multi-processor Communication Mode
    • Using MPCM
  • USART Register Description
    • USART I/O Data Register – UDR
    • USART Control and Status Register A – UCSRA
    • USART Control and Status Register B – UCSRB
    • USART Control and Status Register C – UCSRC
    • USART Baud Rate Registers – UBRRL and UBRRH
  • Examples of Baud Rate Setting
• Universal Serial Interface – USI
  • Overview
  • Functional Descriptions
    • Three-wire Mode
    • SPI Master Operation Example
    • SPI Slave Operation Example
    • Two-wire Mode
    • Start Condition Detector
  • Alternative USI Usage
    • Half-duplex Asynchronous Data Transfer
    • 4-bit Counter
    • 12-bit Timer/Counter
    • Edge Triggered External Interrupt
    • Software Interrupt
  • USI Register Descriptions
    • USI Data Register – USIDR
    • USI Status Register – USISR
    • USI Control Register – USICR
• Analog Comparator
  • ADC Control and Status Register B – ADCSRB
  • Analog Comparator Control and Status Register – ACSR
  • Analog Comparator Multiplexed Input
    • Digital Input Disable Register 0 – DIDR0
• Analog to Digital Converter
  • Features
  • Operation
  • Starting a Conversion
  • Prescaling and Conversion Timing
    • Differential Channels
  • Changing Channel or Reference Selection
    • ADC Input Channels
    • ADC Voltage Reference
  • ADC Noise Canceler
    • Analog Input Circuitry
    • Analog Noise Canceling Techniques
    • Offset Compensation Schemes
    • ADC Accuracy Definitions
  • ADC Conversion Result
    • ADC Multiplexer Selection Register – ADMUX
    • ADC Control and Status Register A – ADCSRA
    • The ADC Data Register – ADCL and ADCH
      • ADLAR = 0
      • ADLAR = 1
    • ADC Control and Status Register B – ADCSRB
    • Digital Input Disable Register 1 – DIDR1
• LCD Controller
  • Features
  • Overview
    • Definitions
    • LCD Clock Cources
    • LCD Prescaler
    • LCD Memory
    • LCD Contrast Controller/Power Supply
    • LCDCAP
    • LCD Buffer Driver
  • Mode of Operation
    • Static Duty and Bias
    • 1/2 Duty and 1/2 Bias
    • 1/3 Duty and 1/3 Bias
    • 1/4 Duty and 1/3 Bias
    • Low Power Waveform
    • Operation in Sleep Mode
    • Display Blanking
    • Port Mask
  • LCD Usage
    • LCD Initialization
    • Updating the LCD
    • Disabling the LCD
    • LCD Control and Status Register A – LCDCRA
    • LCD Control and Status Register B – LCDCRB
    • LCD Frame Rate Register – LCDFRR
    • LCD Contrast Control Register – LCDCCR
    • LCD Memory Mapping
• JTAG Interface and On-chip Debug System
  • Features
  • Overview
  • Test Access Port – TAP
  • TAP Controller
  • Using the Boundary- scan Chain
  • Using the On-chip Debug System
  • On-chip Debug Specific JTAG Instructions
    • PRIVATE0; 0x8
    • PRIVATE1; 0x9
    • PRIVATE2; 0xA
    • PRIVATE3; 0xB
  • On-chip Debug Related Register in I/O Memory
    • On-chip Debug Register – OCDR
  • Using the JTAG Programming Capabilities
  • Bibliography
• IEEE 1149.1 (JTAG) Boundary-scan
  • Features
  • System Overview
  • Data Registers
    • Bypass Register
    • Device Identification Register
      • Version
      • Part Number
      • Manufacturer ID
    • Reset Register
    • Boundary-scan Chain
  • Boundary-scan Specific JTAG Instructions
    • EXTEST; 0x0
    • IDCODE; 0x1
    • SAMPLE_PRELOAD; 0x2
    • AVR_RESET; 0xC
    • BYPASS; 0xF
  • Boundary-scan Related Register in I/O Memory
    • MCU Control Register – MCUCR
    • MCU Status Register – MCUSR
  • Boundary-scan Chain
    • Scanning the Digital Port Pins
    • Scanning the RESET Pin
    • Scanning the Clock Pins
    • Scanning the Analog Comparator
    • Scanning the ADC
  • ATmega169 Boundary- scan Order
  • Boundary-scan Description Language Files
• Boot Loader Support – Read-While-Write Self-Programming
  • Boot Loader Features
  • Application and Boot Loader Flash Sections
    • Application Section
    • BLS – Boot Loader Section
  • Read-While-Write and No Read-While-Write Flash Sections
    • RWW – Read-While-Write Section
    • NRWW – No Read-While-Write Section
  • Boot Loader Lock Bits
  • Entering the Boot Loader Program
    • Store Program Memory Control and Status Register – SPMCSR
  • Addressing the Flash During Self- Programming
  • Self-Programming the Flash
    • Performing Page Erase by SPM
    • Filling the Temporary Buffer (Page Loading)
    • Performing a Page Write
    • Using the SPM Interrupt
    • Consideration While Updating BLS
    • Prevent Reading the RWW Section During Self- Programming
    • Setting the Boot Loader Lock Bits by SPM
    • EEPROM Write Prevents Writing to SPMCSR
    • Reading the Fuse and Lock Bits from Software
    • Preventing Flash Corruption
    • Programming Time for Flash when Using SPM
    • Simple Assembly Code Example for a Boot Loader
    • ATmega169 Boot Loader Parameters
• Memory Programming
  • Program And Data Memory Lock Bits
  • Fuse Bits
    • Latching of Fuses
  • Signature Bytes
  • Calibration Byte
  • Parallel Programming Parameters, Pin Mapping, and Commands
    • Signal Names
  • Serial Programming Pin Mapping
  • Parallel Programming
    • Enter Programming Mode
    • Considerations for Efficient Programming
    • Chip Erase
    • Programming the Flash
    • Programming the EEPROM
    • Reading the Flash
    • Reading the EEPROM
    • Programming the Fuse Low Bits
    • Programming the Fuse High Bits
    • Programming the Extended Fuse Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
    • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Algorithm
    • Data Polling Flash
    • Data Polling EEPROM
    • Serial Programming Characteristics
  • Programming via the JTAG Interface
    • Programming Specific JTAG Instructions
    • AVR_RESET (0xC)
    • PROG_ENABLE (0x4)
    • PROG_COMMANDS (0x5)
    • PROG_PAGELOAD (0x6)
    • PROG_PAGEREAD (0x7)
    • Data Registers
    • Reset Register
    • Programming Enable Register
    • Programming Command Register
    • Flash Data Byte Register
    • Programming Algorithm
    • Entering Programming Mode
    • Leaving Programming Mode
    • Performing Chip Erase
    • Programming the Flash
    • Reading the Flash
    • Programming the EEPROM
    • Reading the EEPROM
    • Programming the Fuses
    • Programming the Lock Bits
    • Reading the Fuses and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
• Electrical Characteristics
  • Absolute Maximum Ratings*
  • External Clock Drive Waveforms
  • External Clock Drive
  • SPI Timing Characteristics
  • ADC Characteristics – Preliminary Data
  • LCD Controller Characteristics – Preliminary Data
• ATmega169 Typical Characteristics – Preliminary Data
• Register Summary
• Instruction Set Summary
• Ordering Information
• Packaging Information
  • 64A
• Table of Contents