Document Outline

• Features
• Pin Configuration
• Description
  • ATtiny11 Block Diagram
  • ATtiny12 Block Diagram
  • Pin Descriptions
    • VCC
    • GND
    • Port B (PB5..PB0)
    • XTAL1
    • XTAL2
    • RESET
  • Clock Options
    • Internal RC Oscillator
    • Crystal Oscillator
    • External Clock
    • External RC Oscillator
• Architectural Overview
  • General-purpose Register File
  • ALU – Arithmetic Logic Unit
  • Flash Program Memory
  • Program and Data Addressing Modes
    • Register Direct, Single Register Rd
    • Register Indirect
    • Register Direct, Two Registers Rd and Rr
    • I/O Direct
    • Relative Program Addressing, RJMP and RCALL
    • Constant Addressing Using the LPM Instruction
  • Subroutine and Interrupt Hardware Stack
  • EEPROM Data Memory
  • Memory Access and Instruction Execution Timing
  • I/O Memory
    • Status Register – SREG
  • Reset and Interrupt Handling
    • Reset Sources
    • Power-on Reset for the ATtiny11
    • Power-on Reset for the ATtiny12
    • External Reset
    • Brown-out Detection (ATtiny12)
    • Watchdog Reset
    • MCU Status Register – MCUSR of the ATtiny11
    • MCU Status Register – MCUSR for the ATtiny12
  • ATtiny12 Internal Voltage Reference
    • Voltage Reference Enable Signals and Start-up Time
  • Interrupt Handling
    • Interrupt Response Time
    • General Interrupt Mask Register – GIMSK
    • General Interrupt Flag Register – GIFR
    • Timer/Counter Interrupt Mask Register – TIMSK
    • Timer/Counter Interrupt Flag Register – TIFR
    • External Interrupt
    • Pin Change Interrupt
    • MCU Control Register – MCUCR
  • Sleep Modes for the ATtiny11
    • Idle Mode
    • Power-down Mode
  • Sleep Modes for the ATtiny12
    • Idle Mode
    • Power-down Mode
  • ATtiny12 Calibrated Internal RC Oscillator
    • Oscillator Calibration Register – OSCCAL
• Timer/Counter0
  • Timer/Counter Prescaler
    • Timer/Counter0 Control Register – TCCR0
    • Timer Counter 0 – TCNT0
• Watchdog Timer
  • Watchdog Timer Control Register – WDTCR
• ATtiny12 EEPROM Read/Write Access
  • EEPROM Address Register – EEAR
  • EEPROM Data Register – EEDR
  • EEPROM Control Register – EECR
  • Prevent EEPROM Corruption
• Analog Comparator
  • Analog Comparator Control and Status Register – ACSR
• I/O Port B
  • Port B Data Register – PORTB
  • Port B Data Direction Register – DDRB
  • Port B Input Pins Address – PINB
  • Port B as General Digital I/O
  • Alternate Functions of Port B
• Memory Programming
  • Program (and Data) Memory Lock Bits
  • Fuse Bits in ATtiny11
  • Fuse Bits in ATtiny12
  • Signature Bytes
  • Calibration Byte in ATtiny12
  • Programming the Flash and EEPROM
    • ATtiny11
    • ATtiny12
    • ATtiny11/12
  • High-voltage Serial Programming
  • High-voltage Serial Programming Algorithm
  • High-voltage Serial Programming Characteristics
  • Low-voltage Serial Downloading (ATtiny12 only)
    • Low-voltage Serial Programming Algorithm
    • Data Polling
  • Low-voltage Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings
  • DC Characteristics – Preliminary Data 
  • External Clock Drive Waveforms
  • External Clock Drive ATtiny11
  • External Clock Drive ATtiny12
  • ATtiny11 Typical Characteristics
  • ATtiny12 Typical Characteristics
• Register Summary ATtiny11
• Register Summary ATtiny12
• Instruction Set Summary
• Ordering Information
• Packaging Information
  • 8P3
  • 8S2