Document Outline

• Features
• Pin Configurations
• Overview
  • Block Diagram
  • Pin Descriptions
    • VCC
    • GND
    • Port A (PA2..PA0)
    • Port B (PB7..PB0)
    • Port D (PD6..PD0)
    • RESET
    • XTAL1
    • XTAL2
• About Code Examples
• Disclaimer
• AVR CPU Core
  • Introduction
  • Architectual Overview
  • ALU – Arithmetic Logic Unit
  • Status Register
  • General Purpose Register File
    • The X-register, Y-register, and Z-register
  • Stack Pointer
  • Instruction Execution Timing
  • Reset and Interrupt Handling
    • Interrupt Response Time
• AVR ATtiny2313 Memories
  • In-System Reprogrammable Flash Program Memory
  • SRAM Data Memory
    • Data Memory Access Times
  • EEPROM Data Memory
    • EEPROM Read/Write Access
    • The EEPROM Address Register
    • The EEPROM Data Register – EEDR
    • The EEPROM Control Register – EECR
    • Atomic Byte Programming
    • Split Byte Programming
    • Erase
    • Write
    • Preventing EEPROM Corruption
  • I/O Memory
    • General Purpose I/O Registers
    • General Purpose I/O Register 2 – GPIOR2
    • General Purpose I/O Register 1 – GPIOR1
    • General Purpose I/O Register 0 – GPIOR0
• System Clock and Clock Options
  • Clock Systems and their Distribution
    • CPU Clock – clkCPU
    • I/O Clock – clkI/O
    • Flash Clock – clkFLASH
  • Clock Sources
  • Default Clock Source
  • Crystal Oscillator
  • Calibrated Internal RC Oscillator
    • Oscillator Calibration Register – OSCCAL
  • External Clock
  • 128 kHz Internal Oscillator
    • Clock Prescale Register – CLKPR
• Power Management and Sleep Modes
  • MCU Control Register – MCUCR
  • Idle Mode
  • Power-down Mode
  • Standby Mode
  • Minimizing Power Consumption
    • Analog Comparator
    • Brown-out Detector
    • Internal Voltage Reference
    • Watchdog Timer
    • Port Pins
• System Control and Reset
  • Resetting the AVR
  • Reset Sources
  • Power-on Reset
  • External Reset
  • Brown-out Detection
  • Watchdog Reset
  • MCU Status Register – MCUSR
  • Internal Voltage Reference
    • Voltage Reference Enable Signals and Start-up Time
  • Watchdog Timer
    • Watchdog Timer Control Register – WDTCR
  • Timed Sequences for Changing the Configuration of the Watchdog Timer
    • Safety Level 1
    • Safety Level 2
• Interrupts
  • Interrupt Vectors in ATtiny2313
• I/O-Ports
  • Introduction
  • Ports as General Digital I/O
    • Configuring the Pin
    • Toggling the Pin
    • Switching Between Input and Output
    • Reading the Pin Value
    • Digital Input Enable and Sleep Modes
  • Alternate Port Functions
    • MCU Control Register – MCUCR
    • Alternate Functions of Port A
    • Alternate Functions of Port B
    • Alternate Functions of Port D
  • Register Description for I/O-Ports
    • Port A Data Register – PORTA
    • Port A Data Direction Register – DDRA
    • Port A Input Pins Address – PINA
    • Port B Data Register – PORTB
    • Port B Data Direction Register – DDRB
    • Port B Input Pins Address – PINB
    • Port D Data Register – PORTD
    • Port D Data Direction Register – DDRD
    • Port D Input Pins Address – PIND
• External Interrupts
  • MCU Control Register – MCUCR
  • General Interrupt Mask Register – GIMSK
  • External Interrupt Flag Register – EIFR
  • Pin Change Mask Register – PCMSK
• 8-bit Timer/Counter0 with PWM
  • Overview
    • Registers
    • Definitions
  • Timer/Counter Clock Sources
  • Counter Unit
  • Output Compare Unit
    • Force Output Compare
    • Compare Match Blocking by TCNT0 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 8-bit Timer/Counter Register Description
    • Timer/Counter Control Register A – TCCR0A
    • Timer/Counter Control Register B – TCCR0B
    • Timer/Counter Register – TCNT0
    • Output Compare Register A – OCR0A
    • Output Compare Register B – OCR0B
    • Timer/Counter Interrupt Mask Register – TIMSK
    • Timer/Counter Interrupt Flag Register – TIFR
• Timer/Counter0 and Timer/Counter1 Prescalers
  • Internal Clock Source
  • Prescaler Reset
  • External Clock Source
  • General Timer/Counter Control Register – GTCCR
• 16-bit Timer/Counter1
  • Overview
    • Registers
    • Definitions
    • Compatibility
  • Accessing 16-bit Registers
    • Reusing the Temporary High Byte Register
  • Timer/Counter Clock Sources
  • Counter Unit
  • Input Capture Unit
    • Input Capture Trigger Source
    • Noise Canceler
    • Using the Input Capture Unit
  • Output Compare Units
    • Force Output Compare
    • Compare Match Blocking by TCNT1 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
    • Phase and Frequency Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 16-bit Timer/Counter Register Description
    • Timer/Counter1 Control Register A – TCCR1A
    • Timer/Counter1 Control Register B – TCCR1B
    • Timer/Counter1 Control Register C – TCCR1C
    • Timer/Counter1 – TCNT1H and TCNT1L
    • Output Compare Register 1 A – OCR1AH and OCR1AL
    • Output Compare Register 1 B – OCR1BH and OCR1BL
    • Input Capture Register 1 – ICR1H and ICR1L
    • Timer/Counter Interrupt Mask Register – TIMSK
    • Timer/Counter Interrupt Flag Register – TIFR
• USART
  • Overview
    • AVR USART vs. AVR UART – Compatibility
  • Clock Generation
    • Internal Clock Generation – The Baud Rate Generator
    • Double Speed Operation (U2X)
    • External Clock
    • Synchronous Clock Operation
  • Frame Formats
    • Parity Bit Calculation
  • USART Initialization
  • Data Transmission – The USART Transmitter
    • Sending Frames with 5 to 8 Data Bit
    • Sending Frames with 9 Data Bit
    • Transmitter Flags and Interrupts
    • Parity Generator
    • Disabling the Transmitter
  • Data Reception – The USART Receiver
    • Receiving Frames with 5 to 8 Data Bits
    • Receiving Frames with 9 Data Bits
    • Receive Compete Flag and Interrupt
    • Receiver Error Flags
    • Parity Checker
    • Disabling the Receiver
    • Flushing the Receive Buffer
  • Asynchronous Data Reception
    • Asynchronous Clock Recovery
    • Asynchronous Data Recovery
    • Asynchronous Operational Range
  • Multi-processor Communication Mode
    • Using MPCM
  • USART Register Description
    • USART I/O Data Register – UDR
    • USART Control and Status Register A – UCSRA
    • USART Control and Status Register B – UCSRB
    • USART Control and Status Register C – UCSRC
    • USART Baud Rate Registers – UBRRL and UBRRH
  • Examples of Baud Rate Setting
• Universal Serial Interface – USI
  • Overview
  • Functional Descriptions
    • Three-wire Mode
    • SPI Master Operation Example
    • SPI Slave Operation Example
    • Two-wire Mode
    • Start Condition Detector
  • Alternative USI Usage
    • Half-duplex Asynchronous Data Transfer
    • 4-bit Counter
    • 12-bit Timer/Counter
    • Edge Triggered External Interrupt
    • Software Interrupt
  • USI Register Descriptions
    • USI Data Register – USIDR
    • USI Status Register – USISR
    • USI Control Register – USICR
• Analog Comparator
  • Analog Comparator Control and Status Register – ACSR
  • Digital Input Disable Register – DIDR
• debugWIRE On-chip Debug System
  • Features
  • Overview
  • Physical Interface
  • Software Break Points
  • Limitations of debugWIRE
  • debugWIRE Related Register in I/O Memory
    • debugWire Data Register – DWDR
• Self-Programming the Flash
  • Performing Page Erase by SPM
  • Filling the Temporary Buffer (Page Loading)
  • Performing a Page Write
  • Addressing the Flash During Self- Programming
    • Store Program Memory Control and Status Register – SPMCSR
    • EEPROM Write Prevents Writing to SPMCSR
    • Reading the Fuse and Lock Bits from Software
    • Preventing Flash Corruption
    • Programming Time for Flash when Using SPM
• Memory Programming
  • Program And Data Memory Lock Bits
  • Fuse Bits
    • Latching of Fuses
  • Signature Bytes
  • Calibration Byte
  • Parallel Programming Parameters, Pin Mapping, and Commands
    • Signal Names
  • Serial Programming Pin Mapping
  • Parallel Programming
    • Enter Programming Mode
    • Considerations for Efficient Programming
    • Chip Erase
    • Programming the Flash
    • Programming the EEPROM
    • Reading the Flash
    • Reading the EEPROM
    • Programming the Fuse Low Bits
    • Programming the Fuse High Bits
    • Programming the Extended Fuse Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
    • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Algorithm
    • Data Polling Flash
    • Data Polling EEPROM
    • Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings*
  • External Clock Drive Waveforms
  • External Clock Drive
• ATtiny2313 Typical Characteristics – Preliminary Data
  • Active Supply Current
  • Idle Supply Current
  • Power-down Supply Current
  • Pin Pull-up
  • Pin Thresholds and hysteresis
  • BOD Thresholds and Analog Comparator Offset
  • Current Consumption of Peripheral Units
  • Current Consumption in Reset and Reset Pulsewidth
• Register Summary
• Instruction Set Summary
• Ordering Information(1)
• Packaging Information
  • 20P3
  • 20S
  • 32M1-A
• Table of Contents