Document Outline

• Chapter 1 USB251x Hub Family Differences Overview
  • Table 1.1 36-pin QFN (6x6x0.5 mm) RoHS Compliant Part Numbers
  • Table 1.2 48-pin QFN (7x7x0.5 mm) RoHS Compliant Part Numbers
  • Table 1.3 64-pin QFN (9x9x0.5 mm) RoHS Compliant Part Numbers
• Chapter 2 General Description
• Chapter 3 Acronyms
• Chapter 4 Block Diagram
  • Figure 4.1 USB251x Hub Family Block Diagram
• Chapter 5 Pin Descriptions
  • 5.1 Pin Configurations and Lists (Organized by Package Type)
    • Figure 5.1 2-Port 36-Pin QFN
    • Figure 5.2 3-Port 36-pin QFN
    • Figure 5.3 4-Port 36-pin QFN
    • Figure 5.4 3-Port 48-Pin QFN
    • Figure 5.5 4-Port 48-Pin QFN
    • Figure 5.6 7-Port 64-Pin QFN
    • Table 5.1 Pin List in Alphabetical Order
  • 5.2 USB251x Pin Descriptions (Grouped by Function)
    • Table 5.2 USB251x Pin Descriptions
  • 5.3 Buffer Type Descriptions
    • Table 5.3 Buffer Type Descriptions
• Chapter 6 LED Usage Description
  • 6.1 LED Functionality
    • 6.1.1 USB Mode 14-Wire
    • 6.1.2 LED Mode Speed Indication
      • Figure 6.1 Dual Color LED Implementation Example
• Chapter 7 Battery Charging Support
  • 7.1 General Description
    • Figure 7.1 Battery Charging via External Power Supply
  • 7.2 USB Battery Charging
    • 7.2.1 Special Behavior of PRTPWR Pins
  • 7.3 Battery Charging Configuration
    • 7.3.1 Battery Charging enabled via EEPROM or SMBus
• Chapter 8 Configuration Options
  • 8.1 Hub
    • 8.1.1 Hub Configuration Options
    • 8.1.2 SMBus or EEPROM Interface
      • Table 8.1 Hub Configuration Options
    • 8.1.3 VBus Detect
  • 8.2 EEPROM Interface
    • 8.2.1 Internal Register Set (Common to EEPROM and SMBus)
      • Table 8.2 Internal Default, EEPROM and SMBus Register Memory Map
      • Table 8.3 PortMap Register for Ports 1 & 2
      • Table 8.4 PortMap Register for Ports 3 & 4
      • Table 8.5 PortMap Register for Ports 5 & 6
      • Table 8.6 PortMap Register for Port 7
    • 8.2.2 I2C EEPROM
    • 8.2.3 In-Circuit EEPROM Programming
  • 8.3 SMBus Slave Interface
    • 8.3.1 SMBus Slave Addresses
    • 8.3.2 Bus Protocols
      • Figure 8.1 Block Write
      • Figure 8.2 Block Read
    • 8.3.3 Invalid Protocol Response Behavior
    • 8.3.4 General Call Address Response
    • 8.3.5 Slave Device Time-Out
    • 8.3.6 Stretching the SCLK Signal
    • 8.3.7 SMBus Timing
    • 8.3.8 Bus Reset Sequence
    • 8.3.9 SMBus Alert Response Address
  • 8.4 Default Configuration Option:
  • 8.5 Default Strapping Options:
  • 8.6 Reset
    • 8.6.1 External Hardware RESET_N
      • Figure 8.3 Reset_N Timing for Default/Strap Option Mode
      • Table 8.7 Reset_N Timing for Default/Strap Option Mode
      • Figure 8.4 Reset_N Timing for EEPROM Mode
      • Table 8.8 Reset_N Timing for EEPROM Mode
      • Figure 8.5 Reset_N Timing for SMBus Mode
      • Table 8.9 Reset_N Timing for SMBus Mode
    • 8.6.2 USB Bus Reset
• Chapter 9 DC Parameters
  • 9.1 Maximum Guaranteed Ratings
  • 9.2 Operating Conditions
    • Figure 9.1 Supply Rise Time Model
    • Table 9.1 DC Electrical Characteristics
    • Table 9.2 Pin Capacitance
• Chapter 10 AC Specifications
  • 10.1 Oscillator/Clock
    • Figure 10.1 Typical Crystal Circuit
    • Figure 10.2 Formula to Find the Value of C1 and C2
    • Figure 10.3 Simplified Form of the Capacitance Formula
    • 10.1.1 SMBus Interface:
    • 10.1.2 I2C EEPROM:
    • 10.1.3 USB 2.0
• Chapter 11 Package Outlines
  • Figure 11.1 36-Pin QFN, 6x6 mm Body, 0.5 mm Pitch
  • Figure 11.2 48-Pin QFN, 7x7 mm Body, 0.5 mm Pitch
  • Figure 11.3 64-Pin QFN, 9x9 mm Body, 0.5 mm Pitch
  • 11.1 Tape and Reel Specifications
    • Figure 11.4 36-Pin Package Tape Specifications
    • Figure 11.5 48-Pin Package Tape Specifications
    • Figure 11.6 36-Pin and 48-Pin Package Reel Specifications