B.8 spi, Appendix c electrical specifications, Table c-1 measurement conditions – Motorola MC9S12GC-Family User Manual
Page 119: C.1 master mode, Figure c-1 spi master timing (cpha=0), Master mode, Figure c-1, Spi master timing (cpha=0)
Device User Guide — 9S12C128DGV1/D V01.05
119
B.8 SPI
Appendix C Electrical Specifications
This section provides electrical parametrics and ratings for the SPI.
In Table C-1 the measurement conditions are listed.
C.1 Master Mode
In Figure C-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.
Figure C-1 SPI Master Timing (CPHA=0)
In Figure C-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Table C-1 Measurement Conditions
Description
Value
Unit
Drive mode
full drive mode
—
Load capacitance C
LOAD,
on all outputs
50
pF
Thresholds for delay
measurement points
(20% / 80%) VDDX
V
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
1
(OUTPUT)
1
9
5
6
MSB IN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
11
4
4
2
10
(CPOL
=
0)
(CPOL
=
1)
3
13
13
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
12