Motorola MC9S12GC-Family - Manual (Page 124)

Device User Guide — 9S12C128DGV1/D V01.05
124
Table C-4 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40˚C to +140˚C, C
LOAD
= 50pF
Num C Rating Symbol Min Typ Max Unit
1 P Frequency of operation (E-clock) f
o
0 25.0 MHz
2 P Cycle time t
cyc
40 ns
3 D Pulse width, E low PW
EL
19 ns
4 D Pulse width, E high 1 PW
EH
19 ns
5 D Address delay time t
AD
8 ns
6 D Address valid time to E rise (PW
EL
–t
AD
) t
AV
11 ns
7 D Muxed address hold time t
MAH
2 ns
8 D Address hold to data valid t
AHDS
7 ns
9 D Data hold to address t
DHA
2 ns
10 D Read data setup time t
DSR
13 ns
11 D Read data hold time t
DHR
0 ns
12 D Write data delay time t
DDW
7 ns
13 D Write data hold time t
DHW
2 ns
14 D Write data setup time (1) (PW
EH
–t
DDW
) t
DSW
12 ns
15 D Address access time (1) (t
cyc
–t
AD
–t
DSR
) t
ACCA
19 ns
16 D E high access time
(1)
(PW
EH
–t
DSR
) t
ACCE
6 ns
17 D Read/write delay time t
RWD
7 ns
18 D Read/write valid time to E rise (PW
EL
–t
RWD
) t
RWV
14 ns
19 D Read/write hold time t
RWH
2 ns
20 D Low strobe delay time t
LSD
7 ns
21 D Low strobe valid time to E rise (PW
EL
–t
LSD
) t
LSV
14 ns
22 D Low strobe hold time t
LSH
2 ns
23 D NOACC strobe delay time t
NOD
7 ns
24 D NOACC valid time to E rise (PW
EL
–t
LSD
) t
NOV
14 ns
25 D NOACC hold time t
NOH
2 ns
26 D IPIPO[1:0] delay time t
P0D
2 7 ns
27 D IPIPO[1:0] valid time to E rise (PW
EL
–t
P0D
) t
P0V
11 ns
28 D IPIPO[1:0] delay time
(1)
(PW
EH
-t
P1V
) t
P1D
2 25 ns
29 D IPIPO[1:0] valid time to E fall t
P1V
11 ns
NOTES :
1. Affected by clock stretch: add N x t
cyc
where N=0,1,2 or 3, depending on the number of clock stretches.