Intel 815 - Manual (Page 100)

AGP/Display Cache Design Guidelines
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100 Intel
®
815 Chipset Platform Design Guide
7.8.2 Display Cache Clocking
The display cache is clocked source-synchronously from a clock generated by the GMCH. The
display cache clocking scheme uses three clock signals.
•
LTCLK clocks the SDRAM devices, is muxed with an AGP signal, and should be routed
according to the flexible AGP guidelines.
•
LOCLK and LRCLK clock the input buffers of the universal platform. LOCLK is an output
of the GMCH and is a buffered copy of LTCLK. LOCLK should be connected to LRCLK at
the GMCH, with a length of PCB trace to create the appropriate clock skew relationship
between the clock input (LRCLK) and the SDRAM
capacitor clock input(s).
The guidelines are illustrated in Figure 48.
Figure 48. Display Cache Input Clocking
disp_cache_in_clk
0.5"
1.5"
15 Ω 1%
15 pF 5%
LOCL
LRCL
GMCH
The capacitor should be placed as close as possible to the GMCH LRCLK pin. To minimize skew
variation, Intel recommends a 1% series termination resistor and a 5% NP0 (also known as C0G)
capacitor, to stabilize the value across temperatures.
In addition to the 15
Ω
, 1% resistor and the
15 pF, 5% NP0 capacitor. The following combination also can be used: 10
Ω
, 1% and 22 pF, 5%
NP0.
7.9 Designs That Do Not Use The AGP Port
Universal platform designs that do not use the AGP port should terminate the AGP pins of the
GMCH. Except for the GPAR pin (that requires a 100 k
Ω
pull-down resistor to ground), the pull-
up or pull-down resistor value should be 8.2 k
Ω
. Any external graphics implementation not using
the AGP port should terminate the GMCH AGP control and strobe signals as recommended in
Section 13.3.2.