Intel 815 - Manual (Page 105)

Integrated Graphics Display Output
R
Intel
®
815 Chipset Platform Design Guide 105
Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections
Graphics Chip
IREF
ball/pin
R
set
Large via or multiple vias straight down to ground plane
Resistor for setting RAMDAC reference current
178
Ω , 1%, 1/16 W, SMT, metal film
Short, wide route connecting resistor to IREF pin
Position resistor
near IREF pin.
No toggling signals
should be routed
near R
set
resistor.
RAMDAC_ref_resistor_place_conn
8.1.4 RAMDAC Layout Recommendations
•
The primary concern with regard to the RGB signal length is that the RGB routes are matched
and routed with the correct impedance. The impedance should be 37.5
Ω
, single-ended trace
to the 75
Ω
, termination resistor. Routing from the 75
Ω
resistor to the video pi-filter and to
the VGA connector should be 75
Ω
impedance.
•
The trace width for the RGB signal should be selected for a 37.5
Ω
impedance (single-ended
route) to the 75
Ω
termination resistor. The 75
Ω
termination resistor should be placed near
the VGA connector.
•
The spacing for each DAC channel routing (i.e., between red and green, green and blue
outputs) should be a minimum of 20 mils.
•
The space between the RGB signal route and other routes should be a minimum of 20 mils for
each DAC route.
•
All RGB signals should be referenced to ground.
•
The trace width for the HSYNC and VSYNC signal routes should be selected for an
approximately 40
Ω
impedance.
•
The spacing between the HSYNC /VSYNC signal routes should be at least 10 mils, preferably
20 mils.
•
The space between HSYNC/VSYNC signal routes and other routes should be at least 10 mils,
preferably 20 mils.
•
Route the HSYNC and VSYNC over the ground plane, if possible. The HSYNC and VSYNC
signals should not route over or near any clock signals or any other high switching routing.
8.1.5 HSYNC/VSYNC Output Guidelines
The HSYNC and VSYNC output of the GMCH may exhibit up to 1.26V P-P noise when driven
high under high traffic system memory conditions. To minimize this, the following is required:
•
Add external buffers to HSYNC and VSYNC.

Examples include: Series 10
Ω
resistor with a 74LVC08