Intel 815 - Manual (Page 41)

Universal Socket 370 Design
R
Intel
®
815 Chipset Platform Design Guide 41
4.3 Power Sequencing on Wake Events
In addition to the mechanism for identifying the processor in the socket, special handling of wake
events is required for the Intel 815 chipset platform that support functionality of the future
0.13 micron socket 370 processors. When a wake event is triggered, the GMCH and the Intel
CK-815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by
setting up the following sequence of events:
1. Power is not connected to the Intel CK-815-compliant clock driver until VTTPWRGD12 is
asserted.
2. Clocks to the ICH stabilize before the power supply asserts PWROK to the ICH. There is no
guarantee this will occur as the implementation for the previous step relies on the 12V supply.
Thus, it is necessary to gate PWROK to the ICH from the power supply while the Intel
CK-815 is given sufficient time for the clocks to become stable. The amount of time required
is a minimum 20 ms.
3. ICH takes the GMCH out of reset.
4. GMCH samples BSEL[1:0]. Intel CK-815 will have sampled BSEL[1:0] much earlier.
4.3.1 Gating of Intel
®
CK-815 to VTTPWRGD
System designers must ensure that the VTTPWRGD signal is asserted before the Intel CK-815-
compliant clock driver receives power. This is handled by having the 3.3V rail of the clock driver
gated by the VTTPWRGD12 reference schematic signal. Unlike previous Intel 815 chipset
designs, the 3.3V standby rail is not used to power the clock as the VTTPWRGD12 reference
schematic signal will cut power to the clock when going into any sleep state. Refer to Figure 17 for
an example implementation.
Figure 17. Gating Power to Intel
®
CK-815
VCC3_3
VDD on CK-815
VTTPW RGD12
MOSFET N
Note: The FET m ust have no m ore than
100 m illiohm s resistance between the
source and the drain.
Gating_Pwr