Intel 815 - Manual (Page 128)

I/O Subsystem
R
128 Intel
®
815 Chipset Platform Design Guide
10.9.5 RTC External RTCRESET Circuit
The ICH RTC requires some additional external circuitry. The RTCRESET (RTC Well Test)
signal is used to reset the RTC well. The external capacitor (2.2
µ
F) and the external resistor
(8.2 k
Ω
) between RTCRESET and the RTC battery (Vbat) were selected to create a RC time
delay, such that RTCRESET will go high some time after the battery voltage is valid. The RC time
delay should be within the range 10–20 ms. When RTCRESET is asserted, bit 2
(RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to 1, and
it remains set until cleared by software. As a result, when the system boots, the BIOS knows that
the RTC battery has been removed.
Figure 67. RTCRESET External Circuit for the ICH RTC
VCC3_3SBY
Vcc RTC
1.0 µF
1 k Ω
2.2 µF
8.2 k Ω RTCRESET
Diode /
battery circuit
RTC_RTCRESET_ext_circ
This RTCRESET circuit is combined with the diode circuit (Figure 67), which allows the RTC
well to be powered by the battery when the system power is not available. Figure 67 shows an
example of this circuitry, which is used in conjunction with the external diode circuit.
10.9.6 RTC-Well Input Strap Requirements
All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC
or pulled down to ground while in G3 state. RTCRST# when configured as shown in Figure 67
meets this requirement. RSMRST# should have a weak external pull-down to ground and
INTRUDER# should have a weak external pull-up to VCCRTC. This prevents these nodes from
floating in G3, and correspondingly prevents ICCRTC leakage that can cause excessive coin-cell
drain. The PWROK input signal should also be configured with an external weak pull-down.