Silicon Laboratories C8051F347 - Manual (Page 142)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
142 Rev. 1.3
15. Port Input/Output
Digital and analog resources are available through 40 I/O pins (48-pin packages) or 25 I/O pins (32-pin
packages). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as gen-
eral-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital
resources as shown in Figure 15.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 15.3 and Figure 15.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 15.1, SFR
Definition 15.2, and SFR Definition 15.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 15.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4). Com-
plete Electrical Specifications for Port I/O are given in Table 15.1 on page 158.
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
XBR0, XBR1, XBR2,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
PnMDOUT,
PnMDIN Registers
UART0
(Int
erna
l Digi
tal
Sign
als)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1
2
6
PCA
CP1
Outputs
2
4
SPI
CP0
Outputs
2
P1
I/O
Cells
P1.0
P1.7
8
P2
I/O
Cells
P2.0
P2.7
8
P3
I/O
Cells
P3.0
8
(Po
rt Lat
ch
es)
P0
8
8
8
8
P1
P2
P3
*P3.1-P3.7 only available on 48-pin
packages
**UART1 only available on
C8051F340/1/4/5/8/A/B devices
UART1**
2
P3.7*
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7*)