Silicon Laboratories SI5375 - Manual (Page 162)

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When an input clock is switched between two clocks that differ in freuqency, the PLL will adjust to the new clock
frequency at a rate that depends on the PLL's loop bandwidth value. This process is the same if a single clock
input abruptly changes frequency. If a PLL has a lower loop bandwidth, its response to such a sudden change in
input frequency will be slower than a PLL with a higher loop bandwidth value. Figure 97 shows a measurement of
the output of an Si5326 during a clock switch from a 100 MHz clock input to a 100 MHz + 100 ppm clock input
(100.01 MHz) with a loop BW of 120 Hz. The horizontal scale is time, in seconds. The vertical scale is the Si5326
output frequency in Hz.
Figure 97. Si5326 Frequency Step Function Response