Silicon Laboratories SI5375 - Manual (Page 79)

Si53xx-RM
Rev. 1.2 79
Before writing a new FLAT[14:0] value, the FLAT_VALID bit must be set to 0 to hold the existing FLAT[14:0] value
while the new value is being written. Once the new value is written, set FLAT_VALID = 1 to enable its use.
To verify a written value into FLAT, the FLAT register should be read after the register is written.
Because the FLAT resolution varies with the frequency plan and selected bandwidth, DSPLLsim reports the FLAT
resolution each time it creates a new frequency plan.
6.7.2.1. Output Phase Adjust (Si5324, Si5327, Si5328, Si5369, Si5374)
Because of its very low loop bandwidth, the output phase of the Si5324, Si5327, Si5328, Si5369, and Si5374 are
not adjustable. This means that the Si5324, Si5327, Si5328, Si5369, and Si5374 do not have any INC or DEC pins
and that they do not have CLAT or FLAT registers.
6.7.3. Independent Skew (Si5324, Si5326, Si5328, Si5368, Si5369, Si5374, and Si5376)
The phase of each clock output may be adjusted in relation to the phase of the other clock outputs, respectively.
This feature is available when CK_CONFIG_REG = 0. The resolution of the phase adjustment is equal to [NI HS/
F
VCO
]. Since F
VCO
is approximately 5 GHz and N1_HS = (4, 5, 6, …, 11), the resolution varies from approximately
800 ps to 2.2 ns depending on the PLL divider settings. Silicon Laboratories' PC-based configuration software
(DSPLLsim) provides PLL divider settings for each frequency translation, if applicable. If more than one set of PLL
divider settings is available, selecting the combination with the lowest N1_HS value provides the finest resolution
for output clock phase offset control. The INDEPENDENTSKEWn[7:0] (n = 1 to 5) register bits control the phase of
the device output clocks. By programming a different phase offset for each output clock, output-to-output delays
can easily be set.
6.7.4. Output-to-output Skew (Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)
The output-to-output skew is guaranteed to be preserved only if the following two register bits are both high:
Register Bit: Location
CKOUT_ALWAYS_ON addr 0, bit 5
SQICAL addr 3, bit 4
In addition, if SFOUT is changed, the output-to-output skew may be disturbed until after a successful ICAL.
Note: CKOUT5 phase is random unless it is used for Frame Sync (See section 6.8).
6.7.5. Input-to-Output Skew (All Devices)
The input-to-output skew for these devices is not controlled.
6.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)
Frame Synchronization Realignment is selected by setting CK_CONFIG_REG = 1. In a typical frame
synchronization application, CKIN1 and CKIN2 are high-speed input clocks from primary and secondary clock
generation cards and CKIN3 and CKIN4 are their associated primary and secondary frame synchronization
signals. The device generates four output clocks and a frame sync output FS_OUT. CKIN3 and CKIN4 control the
phase of FS_OUT. When CK_CONFIG_REG = 1, the Si5368 can lock onto only CKIN1 or CKIN2. CKIN3 and
CKIN4 are used only for purposes of frame synchronization.
The inputs supplied to CKIN3 and CKIN4 can range from 2 to 512 kHz. So that two different frame sync input
frequencies can be accommodated, CKIN3 and CKIN4 each have their own input dividers, as shown in Figure 30.
The CKIN3 and CKIN4 frequencies are set by the CKIN3RATE[2:0] and CKIN4RATE[2:0] register bits, as shown in
Table 35. The frequency of FS_OUT can range from 2 kHz to 710 MHz and is set using the NC5_LS divider
setting. FS_OUT must divide evenly into CKOUT2. For example, if CKOUT2 is 156.25 MHz, then 8 kHz would not
be an acceptable frame rate because 156.25 MHz/8 kHz = 19,531.25, which is not an integer. However, 2 kHz
would be an acceptable frame rate because 156.25 MHz/2 kHz = 78,125.