Silicon Laboratories SI5375 - Manual (Page 89)

Si53xx-RM
Rev. 1.2 89
6.11.7. LOS Algorithm for Reference Clock Input (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369,
Si5374, Si5375, and Si5376)
The reference clock input on the XA/XB port is monitored for LOS. The LOS circuitry divides the signal at XA/XB by
128, producing a 78 kHz to 1.2 MHz signal, and monitors the signal for LOS using the same algorithm as described
in Section “6.11.1. Loss-of-Signal Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368,
Si5369, Si5374, Si5375, and Si5376)”. The LOSX_INT read only bit reflects the state of a loss-of-signal monitor on
the XA/XB port. For the Si5374, Si5375, and Si5376, the XA/XB port refers to the OSC_P and OSC_N pins.
6.11.8. LOL (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
The device has a PLL lock detection algorithm that indicates the lock status on the LOL output pin and the
LOL_INT read-only register bit. The algorithm works by continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock. A retriggerable one-shot is set each time a potential phase cycle slip
condition is detected. If no potential phase cycle slip occurs for the retrigger time, the LOL output is set low,
indicating the PLL is in lock. The LOL pin is held in the active state during an internal PLL calibration. The active
polarity of the LOL output pin is set using the LOL_POL register bit (default active high).
The lock detect retrigger time is user-selectable, independent of the loop bandwidth. The LOCKT[2:0] register bits
must be set by the user to the desired setting. Table 45 shows the lock detect retrigger time for both modes of
operation. LOCKT is the minimum amount of time that LOL will be active.
6.11.9. Device Interrupts
Alarms on internal real-time status bits such as LOS1_INT, FOS1_INT, etc. cause their associated interrupt flags
(LOS1_FLG, FOS1_FLG, etc.) to be set and held. The interrupt flag bits can be individually masked or unmasked
with respect to the output interrupt pin. Once an interrupt flag bit is set, it will remain high until the register location
is written with a “0” to clear the flag.
6.12. Device Reset
Upon powerup or asserting Reset via the RST pin or software, the device internally executes a power-on-reset
(POR) which resets the internal device logic and tristates the device outputs. The device waits for configuration
commands and the receipt of the ICAL = 1 command to start its calibration. Any changes to the CMODE pin
require that RST be toggled to reset the part. The power-up default register values are given in the data sheets for
these parts.
Table 45. Lock Detect Retrigger Time (LOCKT)
LOCKT[2:0] Retrigger Time (ms)
000 106
001 53
010 26.5
011 13.3
100 6.6 (value after reset)
101 3.3
110 1.66
111 .833