High-speed i/o, Input clock buffers, S i 5 3 x x - r m – Silicon Laboratories SI5375 User Manual
Page 94
S i 5 3 x x - R M
94
Rev. 1.2
7. High-Speed I/O
7.1. Input Clock Buffers
Any-Frequency Precision Clock devices provide differential inputs for the CKINn clock inputs. These inputs are
internally biased to a common mode voltage and can be driven by either a single-ended or differential source.
Figure 37 through Figure 41 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note
that the jitter generation improves for higher levels on CKINn (within the limits described in the data sheet).
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
However, either ac or dc coupling is acceptable. Figures 37 and 38 show various examples of different input
termination arrangements.
Unused inputs should have an ac ground connection. For microprocessor-controlled devices, the PD_CKn bits
may be set to shut off unused input buffers to reduce power.
Figure 37. Differential LVPECL Termination
Figure 38. Single-Ended LVPECL Termination
40 k
C
C
±
CKIN
_
CKIN +
V
ICM
300
130
130
3.3 V
82
82
Si53xx
LVPECL
Driver
40 k
40 k
C
C
±
CKIN
_
CKIN +
V
ICM
300
130
3.3 V
82
Si53xx
Driver
40 k