Spectrum Brands MI.20xx - Manual (Page 54)

54 MI.20xx Manual
Overview Clock generation
Clock generation
Overview
The Spectrum boards offer a wide variety of different clock modes to match all the customers needs. All the clock modes are described in
detail with programming examples below. This chapter simply gives you an overview which clock mode to select:
Standard internal sample rate
PLL with internal 40 MHz reference. This is the easiest way to generate a sample rate with no need for additional external clock signals. The
sample rate has a fine resolution.
Quartz and divider
Internal quarz clock with divider. For applications that need a lower clock jitter than the PLL produces. The possible sample rates are restricted
to the values of the divider.
External reference clock
PLL with external 1 MHz to 125 MHz reference clock. This provides a very good clock accuracy if a stable external reference clock is used.It
also allows the easy synchronization with an external source.
External clock
Any clock can be fed in that matches the specification of the board. The external clock signal can be used to synchronize the board on a
system clock or to feed in an exact matching sample rate.
External clock with divider
The externally fed in clock can be divided to generate a low-jitter sample rate of a slower speed than the external clock available.
There is a more detailed description of the clock generation part available as an application note. There some
more background information and details of the internal structure are explained.
Internally generated sample rate
Standard internal sample rate
The internal sample rate is generated in default mode by a PLL and dividers out of an internal 40 MHz frequency reference. In most cases
the user does not need to care on how the desired sample rate is generated by multiplying and dividing internally. You simply write the
desired sample rate to the according register shown in the table below. If you want to make sure the sample rate has been set correctly you
can also read out the register and the driver will give you back the sample rate that is matching your desired one best.
If a sample rate is generated internally, you can additionally enable the clock output. The clock will be available on the external clock con-
nector and can be used to synchronize external equipment with the board.
Example on writing and reading internal sample rate
Minimum internal sample rate
The minimum internal sample rate is limited on all boards to 1 kHz and the maximum sample rate depends on the specific type of board. The
maximum sample rates for your type of board are shown in the tables below.
Register Value Direction Description
SPC_SAMPLERATE 20000 w Defines the sample rate in Hz for internal sample rate generation.
r Read out the internal sample rate that is nearest matching to the desired one.
Register Value Direction Description
SPC_EXTERNOUT 20110 r/w Enables clock output on external clock connector. Only possible with internal clocking. (old name)
SPC_CLOCKOUT 20110 r/w Enables clock output on external clock connector. Only possible with internal clocking. (new name)
SpcSetParam (hDrv, SPC_SAMPLERATE, 1000000); // Set internal sample rate to 1 MHz
SpcSetParam (hDrv, SPC_CLOCKOUT, 1); // enable the clock output of that 1 MHz
SpcGetParam (hDrv, SPC_SAMPLERATE, &lSamplerate); // Read back the sample rate that has been programmed
printf („Samplerate = %d\n“, lSamplerate); // print it. Output should be „Samplerate = 1000000“