SMSC LAN9420 - Manual (Page 79)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 79 Revision 1.22 (09-25-08)
DATASHEET
3.7.5 Resets
The LAN9420/LAN9420i device employs the following resets:
„ Power-On Reset (POR): This reset is asserted on initial application of device power. If the device
is powered from the PCI auxiliary power supply, this reset is asserted for approximately 21mS after
3.3Vaux has reached its operational level. If the device is not powered from the auxiliary supply,
this reset is asserted for approximately 21mS after the main PCI 3.3V supply has reached its
operational level.
„ PCInRST: This is the active-low reset input from the PCI bus. In the D0
U
or D0
A
states, the device
is reset when PCInRST is low. In the D3
HOT
or D3
COLD
states, the device is reset on the
deassertion (low-to-high transition) of PCInRST.
„ D3 Transition Reset (D3RST): This reset occurs when transitioning from the D3
HOT
to D0
U
states.
„ Software Reset (SRST): This reset is initiated by setting the Software Reset (SRST) bit in the Bus
Mode Register (BUS_MODE) . Software Reset does not clear control register bits marked as NASR.
„ PHY Reset via PMT_CTRL (PHY_RST): This reset is asserted by setting the PHY Reset
(PHY_RST) in the Power Management Control Register (PMT_CTRL) . Refer to section Section
3.6.9.1, "PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)," on page 73 for more information.
„ PHY Soft Reset (PHY_SRST): This reset is asserted by writing a ‘1’ to bit 15 of the PHY’s Basic
Control Register. Refer to section
Section 3.6.9.2, "PHY Soft Reset via PHY Basic Control Register
bit 15 (PHY Reg. 0.15)," on page 73 for more information.
The reset map in Table 3.22 shows the conditions under which various modules within
LAN9420/LAN9420i are reset.
Note 3.6 PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3
COLD
wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support
D3
COLD
wake.
Note 3.7 Software Reset does not clear control register bits marked as NASR.
Note 3.8 If PHY was reset on entry to the D3
HOT
, it will be reset when exiting the D3
HOT
. If the PHY
was not reset on entry to the D3
HOT
, it will not be reset when exiting D3
HOT
.
Note 3.9 The Subsystem Vendor ID (SSVID) Subsystem Device ID (SSID) registers (optionally
loaded from the EEPROM) are not reset during this transition.
Table 3.22 Reset Map
BLOCK POR PCInRST D3RST SRST PHY_RST PHY_SRST
PCI PME Logic X Note 3.6
PHY
( Note 3.11 )
X X Note 3.8 X X
( Note 3.10 )
EEPROM Load X X
PCI Configuration
Registers
(except PME registers)
X X X
( Note 3.9 )
MAC X X X X
TX/RX DMACS X X X X
SCSR X X X X
( Note 3.7 )