Clocks, 1 enhanced cpu, 2 clock definitions – NXP Semiconductors P89LPC9321 UM10310 User Manual

Page 21: 1 oscillator clock (oscclk), 3 external crystal oscillator option, 1 low speed oscillator option, Section 2.3, Nxp semiconductors

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UM10310

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© NXP B.V. 2010. All rights reserved.

User manual

Rev. 2 — 1 November 2010

21 of 139

NXP Semiconductors

UM10310

P89LPC9321 User manual

2. Clocks

2.1 Enhanced

CPU

The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.

2.2 Clock

definitions

The P89LPC9321 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources and can also be optionally divided to a slower frequency (see

Figure 8

and

Section 2.10 “CPU Clock (CCLK) modification: DIVM register”

). Note: f

osc

is defined as

the OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two or
four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is

CCLK

2

.

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC9351 provides several user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source.

2.3 External crystal oscillator option

The external crystal oscillator can be optimized for low, medium, or high frequency
crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK
and RTC. Low speed oscillator option can be the clock source of WDT.

2.3.1 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.

Table 4.

Data RAM arrangement

Type

Data RAM

Size (bytes)

DATA

Directly and indirectly addressable memory

128

IDATA

Indirectly addressable memory

256

XDATA

Auxiliary (‘External Data’) on-chip memory that is accessed using
the MOVX instructions

512

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