NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 75)

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User manual Rev. 2 — 1 November 2010 75 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a
write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge
bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
The I 2 C-bus will enter Master Transmitter Mode by setting the STA bit. The I 2 C logic will
send the START condition as soon as the bus is free. After the START condition is
transmitted, the SI bit is set, and the status code in I2STAT should be 08h. This status
code must be used to vector to an interrupt service routine where the user should load the
slave address to I2DAT (Data Register) and data direction bit (SLA+W). The SI bit must
be cleared before the data transfer can continue.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes are 18h, 20h, or
38h for the master mode or 68h, 78h, or 0B0h if the slave mode was enabled (setting
AA = Logic 1). The appropriate action to be taken for each of these status codes is shown
in
Table 73 .
11.6.2 Master Receiver mode
In the Master Receiver Mode, data is received from a slave transmitter. The transfer
started in the same manner as in the Master Transmitter Mode. When the START
condition has been transmitted, the interrupt service routine must load the slave address
and the data direction bit to I
2 C Data Register (I2DAT). The SI bit must be cleared before
the data transfer can continue.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave
mode, the possible status codes are 68H, 78H, or B0H. Refer to
Table 75 for details.
Fig 32. Format in the Master Transmitter mode.
S R/W A DATA DATA
data transferred
(n Bytes + acknowledge)
A A/A P slave address
logic 0 = write
logic 1 = read
from Master to Slave
from Slave to Master
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
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