NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 52)

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User manual Rev. 2 — 1 November 2010 52 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
9.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register ICRAH:ICRAL or ICRBH:ICRBL. The capture event is defined by the
Input Capture Edge Select - ICESx bit (x being A or B) in the CCCRx register. The user
will have to configure the associated I/O pin as an input in order for an external event to
trigger a capture.
A simple noise filter can be enabled on the input capture input. When the Input Capture
Noise Filter ICNFx bit is set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. The inputs are sampled
every two CCLK periods regardless of the speed of the timer.
An event counter can be set to delay a capture by a number of capture events. The three
bits ICECx2, ICECx1 and ICECx0 in the CCCRx register determine the number of edges
the capture logic has to see before an input capture occurs.
When a capture event is detected, the Timer Input Capture x (x is A or B) Interrupt Flag -
TICF2x (TIFR2.1 or TIFR2.0) is set. If EA and the Timer Input Capture x Enable bit -
TICIE2x (TICR2.1 or TICR2.0) is set as well as the ECCU (IEN1.4) bit is set, the program
counter will be vectored to the corresponding interrupt. The interrupt flag must be cleared
manually by writing a logic 0 to it.
When reading the input capture register, ICRxL must be read first. When ICRxL is read,
the contents of the capture register high byte are transferred to a shadow register. When
ICRxH is read, the contents of the shadow register are read instead. (If a read from ICRxL
is followed by another read from ICRxL without ICRxH being read in between, the new
value of the capture register high byte (from the last ICRxL read) will be in the shadow
register).
9.6 PWM operation
PWM Operation has two main modes, asymmetrical and symmetrical. These modes of
timer operation are selected by writing 10H or 11H to TMOD21:TMOD20 as shown in
Section 9.3 “Basic timer operation” .
In asymmetrical PWM operation, the CCU Timer operates in downcounting mode
regardless of the setting of TDIR2. In this case, TDIR2 will always read 1.
Table 41. Event delay counter for input capture
ICECx2 ICECx1 ICECx0 Delay (numbers of edges)
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 7
1 1 1 15