Renesas HD151TS207SS User Manual

Page 2

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HD151TS207SS

Rev.1.00, Apr.25.2003, page 2 of 38

Key Specifications

Supply Voltages: VDD = 3.3 V±5%

CPU clock cycle to cycle jitter = |125ps| (SSC Disabled)

CPU clock group Skew = 100ps

3V66 clock group Skew = 250psmax

PCI clock group Skew = 500psmax

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