C controlled register bit map (cont.) – Renesas HD151TS207SS User Manual
Page 9
HD151TS207SS
Rev.1.00, Apr.25.2003, page 9 of 38
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C Controlled Register Bit Map (cont.)
Table4 CPU Clock Power Management Truth Table
Signal
Pin
PWRDWN#
PWRDWN#
Tristate Bit
Byte2[5:3]
Non-Stop
Outputs
Byte1[5:3] = 1
Note
CPU[2:0]
1
X
Running
CPU[2:0]
0
0
Driven @ Iref x2
See Note1
CPU[2:0]
0
1
Tristate
Note:
1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50
Ω
)
Table5 SRC Clock Power Management Truth Table
Signal
Pin
PWRDWN#
Pin
PCI_STOP#
PCI_STOP#
Tristate Bit
Byte2[6]
PWRDWN#
Tristate Bit
Byte2[7]
Non-Stop
Outputs
Byte1[7] = 1
Stoppable
Outputs
Byte1[7] = 0
Note
SRC
1
1
X
X
Running
Running
SRC
1
0
0
X
Running
Driven @
Iref x6
See Note1
SRC
1
0
1
X
Running
Tristate
SRC
0
X
X
0
Driven @
Iref x2
Driven @
Iref x2
See Note1
SRC
0
X
X
1
Tristate
Tristate
Note:
1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA
Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50
Ω
)
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50
Ω
)
Byte3 Control Register
Bit
Description
Contents
Type
Default
Note
7
PCI_Stop control
0 = Enabled, all stoppable PCI
and SRC clocks are stopped.
1 = Disabled
RW
1
6
PCI_6 Output enable
0 = Disabled, 1 = Enabled
RW
1
5
PCI_5 Output enable
0 = Disabled, 1 = Enabled
RW
1
4
PCI_4 Output enable
0 = Disabled, 1 = Enabled
RW
1
3
PCI_3 Output enable
0 = Disabled, 1 = Enabled
RW
1
2
PCI_2 Output enable
0 = Disabled, 1 = Enabled
RW
1
1
PCI_1 Output enable
0 = Disabled, 1 = Enabled
RW
1
0
PCI_0 Output enable
0 = Disabled, 1 = Enabled
RW
1