Texas Instruments MSP430x4xx User Manual
User’s guide, Msp430x4xx family
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Table of contents
Document Outline
- MSP430x4xx - SLAU056E
- IMPORTANT NOTICE
- Read This First
- Contents
- Chapter 1: Introduction
- Chapter 2: System Resets, Interrupts, and Operating Modes
- Chapter 3: RISC 16-Bit CPU
- Chapter 4: FLL+ Clock Module
- 4.1 FLL+ Clock Module Introduction
- 4.2 FLL+ Clock Module Operation
- 4.2.1 FLL+ Clock features for Low-Power Applications
- 4.2.2 LFXT1 Oscillator
- 4.2.3 XT2 Oscillator
- 4.2.4 Digitally-Controlled Oscillator (DCO)
- 4.2.5 Frequency Locked Loop (FLL)
- 4.2.6 DCO Modulator
- 4.2.7 Disabling the FLL Hardware and Modulator
- 4.2.8 FLL Operation from Low-Power Modes-
- 4.2.9 Buffered Clock Output
- 4.2.10 FLL+ Fail-Safe Operation
- 4.3 FLL+ Clock Module Registers
- Chapter 5: Flash Memory Controller
- 5.1 Flash Memory Introduction
- 5.2 Flash Memory Segmentation
- 5.3 Flash Memory Operation
- 5.3.1 Flash Memory Timing Generator
- 5.3.2 Erasing Flash Memory
- 5.3.3 Writing Flash Memory
- 5.3.4 Flash Memory Access During Write or Erase
- 5.3.5 Stopping a Write or Erase Cycle
- 5.3.6 Configuring and Accessing the Flash Memory Controller
- 5.3.7 Flash Memory Controller Interrupts
- 5.3.8 Programming Flash Memory Devices
- 5.4 Flash Memory Registers
- Chapter 6: Supply Voltage Supervisor
- Chapter 7: Hardware Multiplier
- Chapter 8: DMA Controller
- 8.1 DMA Introduction
- 8.2 DMA Operation
- 8.2.1 DMA Addressing Modes
- 8.2.2 DMA Transfer Modes
- 8.2.3 Initiating DMA Transfers
- 8.2.4 Stopping DMA Transfers
- 8.2.5 DMA Channel Priorities
- 8.2.6 DMA Transfer Cycle Time
- 8.2.7 Using DMA with System Interrupts
- 8.2.8 DMA Controller Interrupts
- 8.2.9 Using the I2C Module with the DMA Controller
- 8.2.10 Using ADC12 with the DMA Controller
- 8.2.11 Using DAC12 With the DMA Controller
- 8.3 DMA Registers
- Chapter 9: Digital I/O
- Chapter 10: Watchdog Timer, Watchdog Timer+
- Chapter 11: Basic Timer1
- Chapter 12: Timer_A
- Chapter 13: Timer_B
- Chapter 14: USART Peripheral Interface, UART Mode
- 14.1 USART Introduction: UART Mode
- 14.2 USART Operation: UART Mode
- 14.3 USART Registers: UART Mode
- UxCTL, USART Control Register
- UxTCTL, USART Transmit Control Register
- UxRCTL, USART Receive Control Register
- UxBR0, USART Baud Rate Control Register 0
- UxBR1, USART Baud Rate Control Register 1
- UxMCTL, USART Modulation Control Register
- UxRXBUF, USART Receive Buffer Register
- UxTXBUF, USART Transmit Buffer Register
- ME1, Module Enable Register 1
- ME2, Module Enable Register 2
- IE1, Interrupt Enable Register 1
- IE2, Interrupt Enable Register 2
- IFG1, Interrupt Flag Register 1
- IFG2, Interrupt Flag Register 2
- Chapter 15: UASRT Peripheral Interface, SPI Mode
- 15.1 USART Introduction: SPI Mode
- 15.2 USART Operation: SPI Mode
- 15.3 USART Registers: SPI Mode
- UxCTL, USART Control Register
- UxTCTL, USART Transmit Control Register
- UxRCTL, USART Receive Control Register
- UxBR0, USART Baud Rate Control Register 0
- UxBR1, USART Baud Rate Control Register 1
- UxMCTL, USART Modulation Control Register
- UxRXBUF, USART Receive Buffer Register
- UxTXBUF, USART Transmit Buffer Register
- ME1, Module Enable Register 1
- ME2, Module Enable Register 2
- IE1, Interrupt Enable Register 1
- IE2, Interrupt Enable Register 2
- IFG1, Interrupt Flag Register 1
- IFG2, Interrupt Flag Register 2
- Chapter 16: OA
- Chapter 17: Comparator_A
- Chapter 18: LCD Controller
- Chapter 19: LCD_A Controller
- 19.1 LCD_A Controller Introduction
- 19.2 LCD_A Controller Operation
- 19.3 LCD Controller Registers
- Chapter 20: ADC12
- 20.1 ADC12 Introduction
- 20.2 ADC12 Operation
- 20.2.1 12-Bit ADC Core
- 20.2.2 ADC12 Inputs and Multiplexer
- 20.2.3 Voltage Reference Generator
- 20.2.4 Auto Power-Down
- 20.2.5 Sample and Conversion Timing
- 20.2.6 Conversion Memory
- 20.2.7 ADC12 Conversion Modes
- 20.2.8 Using the Integrated Temperature Sensor
- 20.2.9 ADC12 Grounding and Noise Considerations
- 20.2.10 ADC12 Interrupts
- 20.3 ADC12 Registers
- Chapter 21: SD16
- 21.1 SD16 Introduction
- 21.2 SD16 Operation
- 21.2.1 ADC Core
- 21.2.2 Analog Input Range and PGA
- 21.2.3 Voltage Reference Generator
- 21.2.4 Auto Power-Down
- 21.2.5 Channel Selection
- 21.2.6 Digital Filter
- 21.2.7 Conversion Memory Registers: SD16MEMx
- 21.2.8 Conversion Modes
- 21.2.9 Conversion Operation Using Preload
- 21.2.10 Using the Integrated Temperature Sensor
- 21.2.11 Interrupt Handling
- 21.3 SD16 Registers
- Chapter 22: SD16_A
- 22.1 SD16_A Introduction
- 22.2 SD16_A Operation
- 22.2.1 ADC Core
- 22.2.2 Analog Input Range and PGA
- 22.2.3 Voltage Reference Generator
- 22.2.4 Auto Power-Down
- 22.2.5 Channel Selection
- 22.2.6 Analog Input Characteristics
- 22.2.7 Digital Filter
- 22.2.8 Conversion Memory Register: SD16MEM0
- 22.2.9 Conversion Modes
- 22.2.10 Using the Integrated Temperature Sensor
- 22.2.11 Interrupt Handling
- 22.3 SD16_A Registers
- Chapter 23: DAC12
- Chapter 24: Scan IF
- 24.1 Scan IF Introduction
- 24.2 Scan IF Operation
- 24.3 Scan IF Registers
- SIFDEBUG, Scan IF Debug Register, Write Mode
- SIFDEBUG, Scan IF Debug Register, Read Mode After 00h Is Written
- SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written
- SIFDEBUG, Scan IF Debug Register, Read Mode After 02h Is Written
- SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written
- SIFCNT, Scan IF Counter Register
- SIFPSMV, Scan IF Processing State Machine Vector Register
- SIFCTL1, Scan IF Control Register 1
- SIFCTL2, Scan IF Control Register 2
- SIFCTL3, Scan IF Control Register 3
- SIFCTL4, Scan IF Control Register 4
- SIFCTL5, Scan IF Control Register 5
- SIFDACRx, Digital-To-Analog Converter Registers
- SIFTSMx, Scan IF Timing State Machine Registers
- Processing State Machine Table Entry (MSP430 Memory Location)