Adv ance informa tion, See figure 40) – Texas Instruments TMS320C6202 User Manual
Page 59
TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
59
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MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP
†‡
(see Figure 40)
NO.
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN
MAX
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P – 1
ns
5
t
(FRH CKRL)
Setup time external FSR high before CLKR low
CLKR int
9
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
1
ns
6
th(CKRL FRH)
Hold time external FSR high after CLKR low
CLKR int
6
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
3
ns
7
t
(DRV CKRL)
Setup time DR valid before CLKR low
CLKR int
8
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
0
ns
8
th(CKRL DRV)
Hold time DR valid after CLKR low
CLKR int
3
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
3
ns
10
t
(FXH CKXL)
Setup time external FSX high before CLKX low
CLKX int
9
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
1
ns
11
th(CKXL FXH)
Hold time external FSX high after CLKX low
CLKX int
6
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
ADV
ANCE INFORMA
TION