Texas Instruments TMS320C6202 - Manual (Page 60)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
60
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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP †‡ (see Figure 40)
NO. PARAMETER
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
1 td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
4 10 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶ C + 1¶ ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2 3 ns
9 td(CKXH FXV) Delay time CLKX high to internal FSX valid
CLKX int –2 3
ns 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid
CLKX ext 3 9
ns
12 tdi (CKXH DXHZ)
Disable time, DX high impedance following last data bit CLKX int –1 4
ns 12 tdis(CKXH-DXHZ)
, g g
from CLKX high CLKX ext 3 9
ns
13 td(CKXH DXV) Delay time CLKX high to DX valid
CLKX int –1 4
ns 13 td(CKXH-DXV) Delay time, CLKX high to DX valid
CLKX ext 3 9
ns
14 td(FXH DXV)
Delay time, FSX high to DX valid
FSX int –1 3
ns 14 td(FXH-DXV)
ONLY applies when in data delay 0 (XDATDLY = 00b)
mode.
FSX ext 3 9
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
¶ C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
ADV
ANCE INFORMA
TION