Xilinx 1000BASE-X - Manual (Page 107)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 107
UG155 March 24, 2008
Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer R
Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer
Virtex-II Pro Devices
Figure 8-7 illustrates sharing clock resources across multiple instantiations of the core on
the same half of the device when using the core with the RocketIO MGT. Figure 8-7
illustrates only two cores; however, more can be added by instantiating the cores using the
block level (from the example design) and sharing userclk, userclk2, and brefclk
across all instantiations. For each core, userclk and userclk2 must always be derived
from the brefclk or refclk used by that core.
Each MGT instantiated has its own independent clock domain synchronous to RXRECCLK
which is placed on local clock routing. Each local clock domain must have area constraints
added to place it in the region of the MGT. See
“Virtex-II Pro RocketIO MGTs for SGMII or
Dynamic Standards Switching Constraints,” page 163 .
When using the fixed routing resources of brefclk, MGTs along the top edge of the
device must use a separate brefclk routing resource to those along the bottom edge of