Xilinx 1000BASE-X - Manual (Page 220)

220 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Appendix E: Rx Elastic Buffer Specifications R
Virtex-II Pro and Virtex-5 Devices
Consider the Virtex-II Pro and Virtex-5 FPGA example, where the shaded area represents
the usable buffer availability for the duration of frame reception.
•
If the buffer is filling during frame reception, there are 52-34 = 18 FIFO locations
available before the buffer reaches the overflow mark.
•
If the buffer is emptying during reception, then there are 30-12 = 18 FIFO locations
available before the buffer reaches the underflow mark.
This analysis assumes that the buffer is approximately at the half-full level at the start of
the frame reception. As illustrated, there are two locations of uncertainty, above and below
the exact half-full mark of 32, resulting from the clock correction decision, and is based
across an asynchronous boundary.
Because there is a worst-case scenario of one clock edge difference every 5000 clock
periods, the maximum number of clock cycles (bytes) that can exist in a single frame
passing through the buffer before an error occurs is:
5000 x 18 = 90000 bytes
Table E-1 translates this into maximum frame size at different Ethernet speeds. At SGMII
speeds lower than 1 Gbps, performance is diminished because bytes are repeated multiple
times (see
“Designing with Client-side GMII for the SGMII Standard” in Chapter 5 ).
Figure E-1: Elastic Buffer Sizes for all RocketIO Transceiver Families
64
34
52 - Overflow Mark
12 - Underflow Mark
64
57 - Overflow Mark
16 - Underflow Mark
CLK_COR_MAX_LAT + 2
CLK_COR_MIN_LAT - 2 30
Virtex-II Pro/Virtex-5
RocketIO Transceiver
Rx Elastic Buffer
Virtex-4 FX
RocketIO Transceiver
Rx Elastic Buffer
Table E-1: Maximum Frame Sizes: RocketIO Transceiver Rx Elastic Buffers
(100ppm Clock Tolerance)
Standard / Speed Maximum Frame Size
1000BASE-X (1 Gbps only) 90000
SGMII (1 Gbps) 90000
SGMII (100 Mbps) 9000
SGMII (10 Mbps) 900