Xilinx 1000BASE-X - Manual (Page 98)

98 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers R
Closely Related Clock Sources
Case 1
Figure 8-2 illustrates a simplified diagram of a common situation where the core, in SGMII
mode, is interfaced to an external PHY device. A common oscillator source is used for both
the FPGA and the external PHY.
If the PHY device sources the receiver SGMII stream synchronously from the shared
oscillator (check PHY data sheet), the RocketIO will receive data at exactly the same rate as
that used by the core. The receiver elastic buffer will neither empty nor fill, having the
same frequency clock on either side.
In this situation, the receiver elastic buffer will not under or overflow, and the elastic buffer
implementation in the RocketIO should be used to save logic resources.
Case 2
Consider again the case illustrated in Figure 8-1 with the following exception: assume that
the clock sources used are both 50 ppm. Now the maximum frequency difference between
the two devices is 100 ppm. It can be shown that this translates into a full clock period
difference every 10000 clock periods, resulting in a requirement for 16 FIFO entries above
and below the half-full point. This provides reliable operation with the RocketIO Rx Elastic
Buffers. Again, however, check the PHY data sheet to ensure that the PHY device sources
the receiver SGMII stream synchronously to its reference oscillator.
RocketIO Logic using the RocketIO Rx Elastic Buffer
When the RocketIO Rx Elastic Buffer implementation is selected, the connections between
the core and the RocketIO as well as all clock circuitry in the system are identical to the
1000BASE-X implementation. For a detailed explanation, see
Chapter 7, “1000BASE-X
with RocketIO Transceivers.”
Figure 8-2: SGMII Implementation using Shared Clock Sources
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
RocketIO
Rx
Elastic
Buffer
TXP/TXN
RXP/RXN
Twisted
Copper
Pair
SGMII Link
10 BASE-T
100BASE-T
1000BASE-T
PHY
FPGA
125MHz -100ppm