Xilinx 1000BASE-X - Manual (Page 85)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 85
UG155 March 24, 2008
RocketIO Transceiver Logic R
Virtex-5 FXT Devices
The core is designed to integrate with the Virtex-5 RocketIO GTX transceiver. Figure 7-4
illustrates the connections and logic required between the core and the GTX transceiver—
the signal names and logic in the figure precisely match those delivered with the example
design when a GTX transceiver is used.
Note: A small logic shim (included in the block-level wrapper) is required to convert between the
port differences between the Virtex-II Pro and Virtex-5 GTX transceiver.
A GTX tile consists of a pair of transceivers. For this reason, the GTX transceiver wrapper
delivered with the core always contains two GTX instantiations, even if only a single GTX
transceiver tile is in use.
Figure 7-4 illustrates a single GTX transceiver tile.
The 125 MHz differential reference clock is routed directly to the GTX transceiver. The GTX
transceiver is configured to output a version of this clock on the REFCLKOUT port: this is
then routed to a DCM.
From the DCM, the CLK0 port (125MHz) is placed onto global clock routing and can be
used as the 125MHz clock source for all core logic: this clock is also input back into the GTX
transceiver on the user interface clock ports rxusrclk2 and txusrclk2.
From the DCM, the CLKDV port (62.5MHz) is placed onto global clock routing and is input
back into the GTX transceiver on the user interface clock ports rxusrclk and txusrclk.
See also “Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints,” page 167 .
Virtex-5 RocketIO GTX Wizard
The two wrapper files immediately around the GTX transceiver pair,
rocketio_wrapper_gtx_tile
and rocketio_wrapper_gtx (see Figure 7-4 ), are
generated from the RocketIO GTX Wizard. These files apply all the gigabit Ethernet
attributes. Consequently, these files can be regenerated by customers and therefore be
easily targeted at ES or Production silicon. Note that this core targets production silicon.
The CORE Generator log file (XCO file) which was created when the RocketIO GTX Wizard
project was generated is available in the following location:
<project_directory>/<component_name>/example_design/transceiver/
rocketio_wrapper_gtx.xco
This file can be used as an input to the CORE Generator to regenerate the RocketIO
wrapper files. The XCO file itself contains a list of all of the GTX Wizard attributes which
were used. For further information, please refer to the Virtex-5 RocketIO GTX Wizard
Getting Started Guide and the CORE Generator Guide, at
www.xilinx.com/support/software_manuals.htm