Rainbow Electronics T89C51RD2 - Manual (Page 32)

Rev. F - 15 February, 2001 32
T89C51RD2
6.6. Serial I/O Port
The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
•
Framing error detection
•
Automatic address recognition
6.6.1. Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 13).
Figure 13. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 15.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.).
Figure 14. UART Timings in Mode 1
RI TI RB8 TB8 REN SM2 SM1 SM0/FE
IDL PD GF0 GF1 POF - SMOD0 SMOD1
To UART framing error control
SM0 to UART mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD D7 D6 D5 D4 D3 D2 D1 D0
FE
SMOD0=1