Rainbow Electronics T89C51RD2 - Manual (Page 38)

38 Rev. F - 15 February, 2001
T89C51RD2
Table 17. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 18. IE Register
IE - Interrupt Enable Register (A8h)
Reset Value = 0000 0000b
Bit addressable
IPH.x IP.x Interrupt Level Priority
0 0 0 (Lowest)
0 1 1
1 0 2
1 1 3 (Highest)
7 6 5 4 3 2 1 0
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number
Bit
Mnemonic
Description
7 EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
6 EC
PCA interrupt enable bit
Clear to disable . Set to enable.
5 ET2
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4 ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3 ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1 ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.