Rainbow Electronics T89C51RD2 - Manual (Page 54)

Rev. F - 15 February, 2001 54
T89C51RD2
They are several software registers described in Table 29
Table 29. Default values
After programming the part by ISP, the BSB must be reset (00h) in order to allow the application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 30 and Table 31
To assure code protection from a parallel access, the HSB must also be at the required level.
The three lock bits provide different levels of protection for the on-chip code and data, when programmed according
to Table 31.
Mnemonic Default value
BSB Boot Status Byte FFh
SBV Software Boot Vector FCh
HSB Copy of the Hardware security byte 18h or 1Bh
SSB Software Security Byte FFh
Copy of the Manufacturer Code
58h
ATMEL Wireless and
Microcontrollers
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: memories
size and type
FCh
T89C51RD2 memories size
Copy of the Device ID # 3: name and revi-
sion
FFh
T89C51RD2 , revision 0
Table 30. Software Security Byte (SSB)
7 6 5 4 3 2 1 0
- - - LB1 - - - LB0
Bit
Number
Bit
Mnemonic
Description
7 -
Reserved
Do not clear this bit.
6 -
Reserved
Do not clear this bit.
5 -
Reserved
Do not clear this bit.
4 LB1
User Memory Lock Bit
See Table 31
1-3 -
Reserved
Do not clear this bit.
0 LB0
User Memory Lock Bit
See Table 31