Rainbow Electronics MAX8903A - Manual (Page 20)

MAX8903A
2A 1-Cell Li+ DC-DC Charger for USB*
and Adapter Power
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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raises the cold threshold, while only slightly raising the
hot threshold. Raising R
TB lowers both the hot and cold
thresholds, while lowering R TB raises both thresholds.
Note that since VL is active whenever valid input power
is connected at DC or USB, thermistor bias current
flows at all times, even when charging is disabled (CEN
= high). When using a 10k
Ω thermistor and a 10kΩ
pullup to VL, this results in an additional 250µA load.
This load can be reduced to 25µA by instead using a
100k
Ω thermistor and 100kΩ pullup resistor.
Power Dissipation
PCB Layout and Routing
Good design minimizes ground bounce and voltage
gradients in the ground plane, which can result in insta-
bility or regulation errors. The GND and PGs should
connect to the power-ground plane at only one point to
minimize the effects of power-ground currents. Battery
ground should connect directly to the power-ground
plane. The ISET and IDC current-setting resistors
should connect directly to GND to avoid current errors.
Connect GND to the exposed pad directly under the IC.
Use multiple tightly spaced vias to the ground plane
under the exposed pad to help cool the IC. Position
input capacitors from DC, SYS, BAT, and USB to the
power-ground plane as close as possible to the IC.
Keep high current traces such as those to DC, SYS,
and BAT as short and wide as possible. Refer to the
MAX8903A Evaluation Kit for a suitable PCB layout
example.
28-PIN 4mm x 4mm THIN QFN
SINGLE-LAYER PCB MULTILAYER PCB
Continuous
Power
Dissipation
1666.7mW
Derate 20.8mW/°C
above +70°C
2286mW
Derate 28.6mW/°C
above +70°C
θ
JA 48°C/W 35°C/W
θ
JC 3°C/W 3°C/W
Table 4. Package Thermal Characteristics
MAX8903A
THIN QFN
4mm x 4mm
TOP VIEW
26
27
25
24
10
9
11
PG DC
DCM
BST IUSB
12
PG
BAT FLT USB BAT THM USUS
1 2
CS
4 5 6 7
20 21 19 17 16 15
CS
LX
GND
IDC
CT
VL
DC
UOK
3
18
28 8 LX DOK
SYS
23 13 ISET SYS
22 14 CEN CHG
+
*EXPOSED PAD
*EP
Pin Configuration
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to
www.maxim-ic.com/packages .
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP T2844-1 21-0139