Rainbow Electronics AT90LS4433 - Manual (Page 29)

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AT90S/LS4433
1042G–AVR–09/02
Timer/Counter Interrupt Flag
Register – TIFR
• Bit 7 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
( T i m e r / C o u n te r1 O v e r f l o w In t e rr u p t En a b l e ) a n d T O V 1 a re s e t ( o n e ) , t h e
Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 advances from $0000.
• Bit 6 – OCF1: Output Compare Flag 1
The OCF1 bit is set (one) when a Compare Match occurs between the Timer/Counter1
and the data in Output Compare Register 1 (OCR1). OCF1 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF1 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG and OCIE1 (Timer/Counter1
Compare Match Interrupt A Enable) and the OCF1 are set (one), the Timer/Counter1
Compare Match Interrupt is executed.
• Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
• Bit 3 – ICF1: Input Capture Flag 1
T he ICF 1 bit is set (o ne) to fl ag an Inp ut C apture Event, i ndi cati ng that th e
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S4433 and always reads as zero.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
( T i m e r / C o u n te r0 O v e r f l o w In t e rr u p t En a b l e ) a n d T O V 0 a re s e t ( o n e ) , t h e
Timer/Counter0 Overflow Interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S4433 and always reads as zero.
Bit 7 6 5 4 3 2 1 0
$38 ($58) TOV1 OCF1 – – ICF1 – TOV0 – TIFR
Read/Write R/W R/W R R R/W R R/W R
Initial Value 0 0 0 0 0 0 0 0