Rainbow Electronics AT90LS4433 - Manual (Page 66)

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AT90S/LS4433
1042G–AVR–09/02
keeps running for as long as the ADEN bit is set and is continuously reset when ADEN
is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following rising edge of the ADC clock cycle. The actual sample-and-hold takes
place 1.5 ADC clock cycles after the start of the conversion. The result is ready and writ-
ten to the ADC Result Register after 13 cycles. In Single Conversion mode, the ADC
needs one more clock cycle before a new conversion can be started (see Figure 47). If
ADSC is set high in this period, the ADC will start the new conversion immediately. In
Free Run mode, a new conversion will be started immediately after the result is written
to the ADC Result Register. Using Free Run mode and an ADC clock frequency of 200
kHz gives the lowest conversion time, 65 µs, equivalent to 15.4 kSPS. For a summary of
conversion times, see Table 21.
Figure 46. ADC Timing Diagram, First Conversion (Single Conversion Mode)
MSB of Result
LSB of Result
ADC Clock
ADSC
Hold Strobe
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2
Dummy Conversion Actual Conversion
Second
Conversion
Table 21. ADC Conversion Time
Condition
Sample Cycle
Number
Result
Ready(Cycle Number)
Total Conversion
Time (Cycles)
Total Conversion
Time (µs)
1st Conversion, Free Run 13.5 25 25 125 - 500
1st Conversion, Single 13.5 25 26 130 - 520
Free Run Conversion 1.5 13 13 65 - 260
Single Conversion 1.5 13 14 70 - 280