Rainbow Electronics AT90LS4433 - Manual (Page 42)

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AT90S/LS4433
1042G–AVR–09/02
Note that in the PWM mode, the ten least significant OCR1 bits, when written, are trans-
ferred to a temporary location. They are latched when Timer/Counter1 reaches TOP.
This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an
unsynchronized OCR1 write. See Figure 34 for an example.
Figure 34. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation, a read from OCR1 will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR1.
When OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on the
next compare match according to the settings of COM11 and COM10. This is shown in
Table 15.
In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter changes direc-
tion at $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter
mode, i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and
global interrupts are enabled. This also applies to the Timer Output Compare1 Flag and
interrupt.
Table 14. Compare1 Mode Select in PWM Mode
COM11 COM10 Effect on OC1
0 0 Not connected
0 1 Not connected
1 0
Cleared on compare match, up-counting. Set on compare match, down-
counting (non-inverted PWM).
1 1
Cleared on compare match, down-counting. Set on compare match, up-
counting (inverted PWM).
Table 15. PWM Outputs OCR = $0000 or TOP
COM11 COM10 OCR1 Output OC1
1 0 $0000 L
1 0 TOP H
1 1 $0000 H
1 1 TOP L