Rainbow Electronics AT90LS4433 - Manual (Page 30)

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AT90S/LS4433
1042G–AVR–09/02
External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The External Interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the External Interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is
held low.
The External Interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector
address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter (two bytes) is pushed onto the Stack, and the Stack
Pointer is decremented by two. The vector is normally a relative jump to the interrupt
routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (two bytes) is
popped back from the Stack, the Stack Pointer is incremented by two and the I-flag in
SREG is set. When the AVR exits from an interrupt, it will always return to the main pro-
gram and execute one more instruction before any pending interrupt is served.
MCU Control Register –
MCUCR The MCU Control Register contains control bits for general MCU functions.
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid having the MCU entering the sleep mode unless it is
the programmer’s purpose, it is recommended that the Sleep Enable SE bit be set just
before the execution of the SLEEP instruction.
• Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to the paragraph “Sleep Modes” below.
Bit 7 6 5 4 3 2 1 0
$35 ($55) – – SE SM ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0