Rainbow Electronics ATtiny12 - Manual (Page 27)

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ATtiny11/12
1006C–09/01
• Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
Timer/Counter Interrupt Flag
Register – TIFR
• Bits 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0
(Ti m e r/ Co u nt e r0 O ver flo w I nt e rru p t E n ab l e ), a n d TOV 0 ar e s e t ( on e ), t h e
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
External Interrupt The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt
will trigger even if the INT0 pin is configured as an output. This feature provides a way of
generating a software interrupt. The external interrupt can be triggered by a falling or ris-
ing edge, a pin change, or a low level. This is set up as indicated in the specification for
the MCU Control Register – MCUCR. When the external interrupt is enabled and is con-
figured as level triggered, the interrupt will trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the MCU Control
Register – MCUCR.
Pin Change Interrupt The pin change interrupt is triggered by any change on any input or I/O pin. Change on
pins PB2..0 will always cause an interrupt. Change on pins PB5..3 will cause an inter-
rupt if the pin is configured as input or I/O, as described in the section “Pin Descriptions”
on page 5. Observe that, if enabled, the interrupt will trigger even if the changing pin is
configured as an output. This feature provides a way of generating a software interrupt.
Also observe that the pin change interrupt will trigger even if the pin activity triggers
another interrupt, for example, the external interrupt. This implies that one external
event might cause several interrupts.
The values on the pins are sampled before detecting edges. If pin change interrupt is
enabled, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt.
Bit 7 6 5 4 3 2 1 0
$38 - - - - - - TOV0 - TIFR
Read/Write R R R R R R R/W R
Initial Value 0 0 0 0 0 0 0 0