Rainbow Electronics ATtiny12 - Manual (Page 26)

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ATtiny11/12
1006C–09/01
interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $001. See also “External Interrupts.”
• Bit 5 - PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the interrupt on pin change is enabled. Any change on any input or I/O pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from
program memory address $002. See also “Pin Change Interrupt.”
• Bits 4..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
General Interrupt Flag
Register – GIFR
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
• Bit 6 - INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical one to it. The flag is always cleared when INT0 is configured
as level interrupt.
• Bit 5 - PCIF: Pin Change Interrupt Flag
When an event on any input or I/O pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to
the interrupt vector at address $002. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
Timer/Counter Interrupt Mask
Register – TIMSK
• Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$003) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag
(Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
Bit 7 6 5 4 3 2 1 0
$3A - INTF0 PCIF - - - - - GIFR
Read/Write R R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$39 - - - - - - TOIE0 - TIMSK
Read/Write R R R R R R R/W R
Initial Value 0 0 0 0 0 0 0 0