3 output format, 4 test pattern, 5 contrast expansion – Rainbow Electronics ATMOS™ 2M60 User Manual

Page 12

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ATMOS -2M60/2M30 [Preliminary]

5.3

Output Format

The data format available on the Camera Link output interface is programmable via the serial
interface.

Note:

The pixel depth is set by default at 12-bit, it can be set to 10 or 8-bit. The assignment for each con-
figuration comply with the specifications of the Camera Link interface standard. See register Mode
Control bits [3:2] @ 204H, Internal Register Mapping

page 16

.

5.4

Test Pattern

In normal mode, the digital video signal from the sensor is available on the Camera Link output
interface. For test purposes a digital pattern is generated and is available instead of the video
signal in the Camera Link output interface. The pattern can be fixed or sliding. The fixed digital
pattern is ramp-up from 960 LSB code to 2008 LSB code (line width). The same pattern is
shown for each line:

Figure 5-1.

Test Pattern View

The sliding pattern starts with the fixed pattern, the first code of each line is then incremented by
two on each frame. It is useful to validate the connection to the acquisition system before the
adjustment settings of the image capture. The output format is the only processing which applies
to the test pattern. See

”Digital Processing Synoptic” on page 14

.

See register Mode Control bits [1:0] @ 204H, Internal Register Mapping on

page 16

.

5.5

Contrast Expansion

This processing does not apply to the test pattern. The digital gain and offset can be adjusted via
the serial communication in order to focus on a particular part of the dynamic range.

• Gain adjusted from x1 to x32.875: code 0 to 255

• Step 0.125

• Nominal gain (factory configuration):

×

1

See register Digital Gain @ 242H, Internal Register Mapping on

page 16

.

• Offset adjusted from -4096 to +4095: code 0 to 8191 in 2's complement

• Step 1

• Nominal offset (factory configuration): 0

See register Digital Offset @ 244H, Internal Register Mapping on

page 16

.

See register Processing Control bits [1:0] @ 202H, Internal Register Mapping on

page 16

.

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